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Thermal Integrity Challenges and Solutions of Silicon Interposer Design

In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation will cover thermal hotspots, mechanical stresses induced by thermal issues, and methods for capturing these problems with simulation and virtual prototyping, with a focus on designs that utilize silicon interposers.


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About this Webinar

Thermal integrity and thermal-induced mechanical issues are becoming essential for the new generation of 2.5D/3D-IC with closely packed chiplets on an interposer, package, and board due to strong cross-die thermal coupling. Traditionally, on-chip thermal sensors are placed on potential hotspots to detect real-time temperature to avoid thermal throttling via the Dynamic Thermal Management (DTM) technique. However, it is challenging to cover all hotspot locations of a complicated stacked-die system to place the sensors. This presentation will introduce the key technologies from Ansys to address pre-silicon thermal integrity simulation and mechanical stress analysis. 

What You Will Learn

  • Why do emerging 2.5D/3D-ICs with silicon interposer pose thermal integrity challenges?
  • What are the available technologies and methodologies in thermal integrity simulation?
  • Presentation of several actual case studies using Ansys multiphysics tools
  • New research regarding EDA solutions for thermal integrity

Who Should Attend

All 3D-IC designers



Dr. Lang Lin is a principal product manager of Ansys, based in San Jose, California. He develops 3D-IC multiphysics simulation and security verification methodologies for worldwide semiconductor customers. Before joining Ansys, Dr. Lin worked for Intel Corp. as a design engineer. He has published 50+ technical papers and patents and served as a reviewer, program committee, or tutorial speaker at IEEE conferences such as HOST, ICCAD, DAC, and ASPDAC.