Timing Is of the Essence: Variability-aware and SPICE-accurate Timing Closure

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield.

Learn how ANSYS Path FX with its unique variation-aware technology can save you from the gross inaccuracies of your current methods of modeling variation. The Path FX solution seamlessly fits into existing design flows to complement traditional timing signoff methodologies. It helps lower design costs and increase yield with a SPICE-accurate solution that runs about a 100-times faster. This white paper addresses: SPICE-accurate process variation especially at low voltage; SPICE-accurate voltage variation, including clock jitter due to IR drop; and a methodology shift in modeling chip-level aging that is easier, faster and more accurate than current approaches.

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