This webinar highlights the latest embedded software innovations in Ansys 2022 R1 for verification and validation (V&V). It illustrates the highly increased efficiency of the Ansys SCADE-based V&V workflow, focusing on the new, unique Model Coverage Assistance capability and Design Verifier enhancements for formal proof.
The coverage analysis assistant is available both at the design phase to speed up the detection of uncoverable parts of the model and at the testing phase, to provide either input scenarios to improve model (and code) coverage or justification templates in case of uncoverability.
The Design Verifier now allows to analyze imported operators and reduce analysis time using abstraction operators.
- How to speed-up complex and time-consuming model and code coverage activities for embedded software
- How the new SCADE coverage analysis assistant can revolutionize model-based testing processes
- How SCADE helps improve software quality and robustness by supporting and streamlining formal methods in the embedded software development