Ansys RedHawk-SC is the proven industry leader for power noise and reliability signoff for your SoC designs. With a track record of thousands of designs in silicon, RedHawk-SC enables you to create high-performance SoCs that are still power efficient and reliable against thermal, electromigration (EM) and electrostatic discharge (ESD) issues for markets such as mobile, communications, high-performance computing, automotive and internet of things (IoT).

RedHawk-SC is a next-generation solution built on Ansys SeaScape, the world's first custom-designed, big data architecture for electronic system design and simulation. SeaScape provides per-core scalability, flexible design data access, instantaneous design bring-up, MapReduce-enabled analytics and many other revolutionary capabilities.

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ANSYS RedHawk-SC is the new standard for power noise and reliability sign-off for next generation designs that is production proven and silicon validated. The underlying elastic compute architecture has the scalability to solve the largest chips within a few hours. Big data analytics enable rapid data mining to drive actionable outcomes and optimization. RedHawk-SC can explore thousands of switching scenarios overnight, and prioritizes large numbers of vector sets by analyzing multiple different parameters. RedHawk-SC is built for multi-site collaboration, empowering you to simultaneously view, debug and explore design and simulation data. With RedHawk-SC, you can load the largest designs within seconds, run complex multi-variable analytics, drive design optimization and achieve faster design closure.

RedHawk-SC Platform
RedHawk-SCTM Platform

Elastic Compute Scalability
With unparalleled scalability across thousands of cores using big data techniques, ANSYS RedHawk-SC helps you sign off a billion-plus instance designs within a few hours on commodity hardware. No dedicated machines are needed — RedHawk-SC runs the largest designs, using low memory cores, even if they reside on different machines.

When RedHawk-SC launches, it starts working as soon as a single core is available. It proportionately speeds up as more cores become available, and has the resiliency to recover should any core or machine become unresponsive. Because RedHawk-SC can utilize unused cores, it increases utilization rates of compute farms, thereby decreasing overall hardware costs; unlike other tools it does not require dedicated hardware, even for the largest designs.

Large design workflows involve integrating multiple blocks with different degrees of completion through the design lifecycle. RedHawk-SC has adaptive partitioning to handle varying levels of design details (black-box to full) with optimal runtime. Large designs also require high compute resources, with hundreds of CPU cores on a network. With an increased number of CPU cores, the risk of CPU failure during analysis increases. RedHawk-SC’s built-in resiliency capabilities help jobs to recover automatically from such network failure issues.

This elastic scalability is what enables RedHawk-SC to process designs of unprecedented size with flat accuracy, high resolution extracted networks and multiple scenarios.

Big Data Analytics
Big data analytics enable rapid data mining and analytics to drive actionable outcomes and optimization. Using custom data analytics, you can identify and prioritize only those design fixes that are key to product success. Custom analytics powered by MapReduce enable you to query the largest designs in minutes. RedHawk-SC offers combined display and analytics across multiple views; heat maps for design quality check analysis; combined analysis across multiple scenarios for coverage analysis and issue diagnostics; and custom heat-map support.

RedHawk-SC Architecture
RedHawk-SC Architecture

Accelerated Design Closure
With the increasing number of cores in CPU and GPU sub-systems in next-generation SoCs, it is crucial to understand and isolate the switching combination that can generate a chip-package-PCB resonance condition resulting in catastrophic voltage-drop-induced failure. RedHawk-SC leverages patented algorithmic approaches customized on the ANSYS SeaScape architecture to perform rapid design evaluation by exploring thousands of switching possibilities, and highlighting specific operating modes that should be avoided either through design or software level changes.

Design teams often struggle with understanding which vectors to use and which cycles within these vectors to simulate for signoff. Using RedHawk-SC’s multiphysics analytics, you can now “score” vectors across multiple parameters to identify the appropriate vectors and, more crucially, isolate cycles within these vectors that are important for power noise signoff. This will help you perform targeted simulations while getting meaningful coverage.

Critical vector selection based on multiple different parameters
Critical vector selection based on multiple different parameters

Multiphysics Optimization
For advanced process nodes,  margin-based design methodologies force overdesign and guardbanding, resulting in larger die sizes and increased design schedules. With RedHawk-SC you can perform multi-scenario simulations and run multiphysics analytics all within your design ECO cycle. With this methodology, you can target fixes in high stress areas while reducing overdesign in other parts of the chip. The design fix suggestions can be done quickly and efficiently through standard interfaces with existing place and route solutions. This has been proven over multiple successful tapeouts to reduce power consumption and die size while meeting performance and reliability targets.

Multi-site Collaboration using Thin Client Support
RedHawk-SC is built for multi-site collaboration and effective design analysis. Users across multiple sites can simultaneously view, debug and explore design and simulation results. You can bring up the largest designs in small memory machines in minutes and simultaneously view and optimize the same database across multiple sites.

Instantaneous Result and Native Layout Viewing with Full Hierarchical Support
RedHawk-SC allows simultaneous power and signal line analysis on a full-chip SoC with full hierarchical support. You can interactively view and monitor progress of the analysis while simulation is ongoing. You can also debug results with current heat maps that display nodes/edges for clear identification of the extracted circuit for advanced current flow and EM modeling.

Machine Learning Support
Machine learning support enables a wide range of applications, such as identifying missed systematic design weaknesses and automating time-consuming rigorous manual procedures. This is done by aggregating key insights across different designs using continuing and prior simulation and design data.

Comprehensive Dynamic Analysis Coverage
RedHawk-SC offers you the most comprehensive dynamic analysis coverage by enabling you to sign off SoCs with confidence using a wide variety of simulation modes — RTL and gate vectors; smart vectorless analysis for functional and scan mode; mix-mode simulation (vectorless + VCD); and frequency-aware vectorless to stress system level PDN, power-transient and power-up analysis.

RedHawk-SC introduces a novel no-propagation-vectorless™ (NPV) dynamic analysis approach that enables you to efficiently identify power grid weaknesses in the absence of simulation vectors. This approach can be used at any level of hierarchy from block to full-chip, on multimillion to billion instance designs. NPV can also be used to create multiple sets of scenarios to increase switching coverage of designs, while maintaining power targets and distribution — various power distribution schemes such as cell-type, block and macro are supported. With NPV, you can increase traditional single-scenario switching coverage from 10–15% to >90% employing tens of scenarios.

RedHawk-SC can now perform automatic time-slicing of large vectors to simulate portions of the vector in parallel, and collate results for simplicity. This has enabled automotive and mobile customers to analyze large workloads on their chips with significant improvement in runtime.

Chip Package Co-optimization
You can perform chip-package co-optimization by modeling the package and board for system-aware chip signoff and enabling chip power and thermal modeling for chip-aware system signoff for advanced multi-die packaging technologies.

Electromigration and ESD Signoff
RedHawk-SC offers comprehensive electrostatic discharge (ESD) analysis of HBM and CDM ESD events and power and signal electromigration (EM) analysis, in addition to advanced thermal-aware EM and statistical EM budgeting, which is a pressing reliability problem for sub-16nm designs.

Silicon-proven Signoff Leader
RedHawk-SC is known for its silicon-proven accuracy for SoC power integrity and reliability signoff and is supported by certifications from all major foundries for manufacturing processes down to 4nm/3nm.

Capabilities

  • Chip-Package Co-Analysis

    Chip-package-system co-analysis provides superior simulation accuracy and greater design insight than current independent analyses of chip and package.

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  • Thermal-Aware EM

    Redhawk identifies thermal integrity and thermal-aware reliability issues, which can have a significant impact on power (leakage), IR, timing and electromigration (EM), especially in automobile applications.

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  • Capacity and Performance

    RedHawk offers you the capacity and performance to simulate designs having over 1 billion instances using advanced Distributed Machine Processing (DMP) techniques.

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  • Silicon-Validated Signoff Accuracy

    Provides foundry-certified accuracy for the reduced noise margins and higher voltage drops typical for FinFET designs.

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  • Power Noise Impact on Timing

    RedHawk helps you understand the impact of dynamic voltage drop on timing for clock and critical paths using full-chip-level timing-impact analysis in a SPICE-based sign-off simulation.

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  • Integrity and Reliability of Advanced IC Packaging

    Encapsulating chips within a 2.5-D or 3D package improves power, performance and form factor. Redhawk is qualified for the 2.5-D and 3D package reference flows.

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