ANSYS RedHawk Capabilities

Chip-Package Co-Analysis

In electronic systems targeted for mobile handsets or servers, ICs such as processors and memories execute the application and data processing functions, consuming the most power. These ICs also transfer the largest amount of data to and from their I/O circuits, and have the greatest detrimental power, thermal and EMI signatures.

The power consumed by an IC is directly related to its supply voltage. With the threshold voltage not scaling as well, the gap between the supply and threshold voltages shrinks, thereby reducing the noise margin.

As technology scales, the drive for reduced cost and power complicates the design of the power delivery network (PDN) at chip and package levels because of increased package impedance. This reduces the voltage to detrimental levels on the chip.

RedHawk-CPA enables you to seamlessly import package layout and consider the decaps and inductance for package-aware and accurate on-chip static IR drop and AC hotspot analyses.

Chip-Package Co-Analysis


Thermal-Aware EM

ESD and power/ground and signal EM are the two most pressing reliability problems at the sub-16nm level. The accuracy and coverage of EM and ESD analyses are extremely important. As currents in wires increase, operating voltages decrease and EM limits shrink. With FinFETs, self-heating adds to the thermal issue. With applications such as automotive, it is critical to understand, analyze and optimize every IC design for proper thermal behavior.

RedHawk provides full support for thermal-aware power/ground and signal line EM verification, accurately analyzing EM violations while minimizing false positives, even for the advanced FinFET-based designs. When used in conjunction with ANSYS PathFinder, RedHawk can perform SoC-level ESD integrity analysis, providing connectivity and interconnect failure checks for all current flow pathways (wires and vias) from an ESD event (HBM, CDM). RedHawk is foundry-certified for power EM, signal EM and SoC ESD sign-off.

Thermal-Aware EM


Capacity and Performance

Today’s system on chips (SoCs) have greater integration of content and use advanced process technologies. As a consequence, the number of design parameters that have to be considered are growing rapidly. This creates a performance bottleneck for analysis runs that take days at best and, in the worst case, do not run at all.

RedHawk offers you the capacity and performance to simulate designs over 1 billion instances using advanced Distributed Machine Processing (DMP) techniques. DMP maintains sign-off accuracy that can be obtained only through flat simulation.

DMP also takes advantage of the increasing processing power and memory capacity available in a private machine cluster to simulate the entire chip’s RLC network matrices, along with fully distributed and cross-coupled package models. By performing full-chip flat analysis, RedHawk maintains sign-off accuracy for dynamic voltage drop, EM and ESD.

Capacity and Performance


Silicon-Validated Sign-off Accuracy

At the chip-level, the use of the latest process technology is typically driven by the need for one or more of the following: faster performance, greater bandwidth, higher performance-to-power ratio and reduced die size. The newer the process technology, the higher the opportunity for failure, and the greater the cost of design mistakes. This is why sign-off certification is important.

TSMC and ANSYS engineers worked very closely together since 2006 on every process technology to ensure that all new rules, parameters and requirements for the process were considered by ANSYS solutions, and that the results correlated to their reference results from test silicon.

ANSYS solutions are certified for the advanced 7nm process. Key capabilities within ANSYS that enabled the certification include support for coloring, accurate modeling of multi-bit multi-height (MBMH) cells, modeling of special via structures, and associated complex electromigration (EM) rules. This level of certification criteria helps to ensure first pass silicon success.

Silicon-Validated Sign-Off Accuracy


Power Noise Impact on Timing

Dynamic voltage drop in a design has the potential to impact clock jitter, critical paths and timing. In today’s designs with multiple clock and power domains, it is important to evaluate clock tree performance, and identify and analyze jitter, signal crosstalk and timing problems prior to sign-off.

RedHawk’s fast full-chip-level timing-impact analysis helps you evaluate clock tree performance. In addition, it enables you to identify parts of the circuit that could be affected by jitter, signal crosstalk and timing problems. RedHawk’s SPICE-accurate sign-off simulation helps you to identify and take steps to eliminate issues on clock trees, affected critical paths and circuit timing.

Power Noise Impact on Timing


Integrity and Reliability of Advanced IC Packaging

An ongoing strategy for engineers designing integrated circuits (ICs), including system on chips (SoC), is to use integration and miniaturization to increase performance and bandwidth while reducing power and footprint.

For any package technology, integrity, reliability and cost are three major vectors that need to be optimized. The integrity vector spans power and signal noise. Reliability deals with thermal, electromigration (EM), electrostatic discharge (ESD), electromagnetic interference (EMI) and thermal-induced structural stress issues. Cost factors into almost all applications, especially for consumer products and Internet of Things (IoT) devices. Optimizing and ensuring the integrity and reliability of a chip (at a die-level) in the context of its respective package, board and system is very complex, and it only increases when multiple dies are involved.

ANSYS solutions enable you to make sure your advanced 2.5-D or 3-D-IC package designs meet the integrity and reliability requirements at the chip, package and system levels.

Integrity and Reliability of Advanced IC Packaging