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How to Design 2.5D/3D IC Architectures in a Single Workflow

Ansys RedHawk-SC electrothermal warpage map of a 3D package due to thermal stress

Electronics designs for leading applications like artificial intelligence (AI), machine learning (ML), 5G mobile and high-performance computing (HPC) require tens of billions of transistors — often more than can fit on a single integrated circuit (IC).

IC packages frequently incorporate significant amounts of memory and analog functionality, like wireless communication blocks, that call for different kinds of transistor technologies.

As a result, the electronics industry has evolved to pursue increased scalability by stacking multiple silicon die into a single 3D integrated package.

Engineers need the right tools to design these 2.5D and 3D IC architectures so they can reach the performance, power, size and cost requirements of these leading-edge applications.

To this end, Ansys software partner, Synopsys, recently released its 3DIC Compiler. It is a new tool that consolidates all required capabilities for 2.5D and 3D design into a single environment. The innovative environment also helps teams plan, explore, design, implement, assess and sign off popular foundry architectures for multi-die integration.

Ansys RedHawk and Ansys RedHawk-SC and elements of the Ansys chip-packaging system are integrated into 3DIC Compiler, to provide comprehensive power and thermal integrity analysis for the combined chip-package system, including cosimulation of interposers and redistribution layers. These Ansys tools provide 3DIC Compiler with detailed reports and visualizations of electromigration (EM), voltage drop (IR), system power integrity, thermal maps and mechanical stress due to thermal expansion.

Automatic back-annotation between Ansys RedHawk and Ansys RedHawk-SC and 3DIC Compiler will speed up the convergence to an optimal design with the least number of iterations.

How Ansys RedHawk Integrates Into Synopsys 3DIC Compiler

Synopsys’ Fusion Compiler physical implementation tool is already integrated within Ansys RedHawk-SC through the RedHawk Analysis Fusion option from Synopsys. This can also be used with 3DIC Compiler for basic power integrity analysis.

Popular stacking techniques using either a silicon interposer (2.5D) or direct stacking of die on die (3D)

Customers can perform more detailed and comprehensive analyses, like thermal analysis, mechanical stress analysis, interposer extraction and full power distribution network (PDN) cosimulation, by acquiring licenses of Ansys RedHawk and Ansys RedHawk-SC and Ansys chip-packaging system.

The Synopsys 3DIC Compiler and Ansys RedHawk-SC integration delivers a comprehensive and signoff-accurate design workflow for exploring, designing and verifying the most advanced 2.5D/3D packaging systems available today.

To learn more about Ansys 2.5D/3D IC analysis capabilities and tools, please see Ansys Chip-Package Co-analysis and Ansys Achieves Certification for TSMC Advanced 3D Chips Stacking Technology.