This hands-on course is designed to teach you how to use the VeloceRF synthesis engine to generate optimal, guaranteed DRC-clean and DfM-correct parametric cells for any process node, down to 3nm within a traditional custom IC design flow.
The course also introduces you to the VeloceRF user interface (UI) to synthesize inductors, transformers, tcoils and transmission lines, assess their performance and integrate them into the IC design flow (layout, schematic, LVS/LPE, circuit simulation).
- Basic understanding of custom IC design flows and electromagnetics
- Some general familiarity with EM solvers
- No prior knowledge or experience of VeloceRF is required
Chip IP/SoC/CAD Engineers & Designers
Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops.