Skip to Main Content

Ansys RaptorX: How to use RaptorX for the Signal Integrity (SI) Signoff of Silicon Interposers

Course Overview

This workshop will teach you how to perform signal and power integrity analysis of silicon interposers using Ansys RaptorX in standalone mode. You will learn how to assign ports on signal, power, and ground nets for S-parameter extraction, including how to efficiently include deep trench capacitors in the extracted model. This will enable you to perform any electromagnetic extraction required for modelling silicon interposers. The workshop will include a live session where ports are placed and a small section of a silicon interposer signal, power, and ground nets will be extracted.


It is highly recommended you understand the following:

  • IC design
  • Different die packaging
  • UNIX and Linux
  • S-parameters
  • RaptorX (Recommended but not essential)

Teaching Method

Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops. 

Learning Outcome

Following completion of this course, you will be able to:

  • Place ports suitable for the extraction of signal and power nets on interposers.
  • Include the extraction of deep trench capacitors.
  • Perform a RaptorX analysis and get S-parameters of fully coupled signal and power nets on an interposer.


 Available Dates

Learning Options

Training materials for this course are available with a Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.


This is a 1-day classroom course covering both lectures and workshops. For virtual training, this course is covered over 1 x 2-hour sessions lectures only.

Virtual Classroom Session 1

  • Importance of EM extraction for silicon interposers
  • What is RaptorX?
  • Modeling deep trench capacitors with RaptorX
  • Performing signal integrity analysis of silicon interposers with RaptorX
  • Overview of test case layout
  • Validation of accuracy
  • Live Session