This hands-on course is designed for new or current Ansys Pathfinder users who may want to refresh their skills or get training on the following topics:
- Configure and run static ESD layout checks prescribed by foundry or determined by design teams.
- Debug results to identify grid weakness along esd discharge paths that could potentially cause ESD induced failures.
- Basic understanding static ESD layout checks.
Chip IP/SoC/CAD Engineers & Designers responsible for ESD signoff.
Explanation of training slides and demo to help user get an overview on how to configure and use tool.