Skip to Main Content

Ansys PathFinder
Getting Started

Course Overview

Ansys PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.


  • Basic understanding of Ansys Totem and ESD concepts expected.

Teaching Method

Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops.

Learning Outcome

Following completion of this course, you will be able to:

  • You will gain an understanding of Totem PathFinder layout-based analysis and a proficiency in both running analyses and debugging ESD-related issues using the GUI Wizard-based flow.
  • Understand the basics of Ansys Totem and ESD concepts expected.

 Available Dates

Learning Options

Training materials for this course are available with an Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.


This is a 1-day classroom course covering both lectures and workshops. For virtual training, this course is covered over 4-hours, including lectures and demo.

  • PathFinder Overview
  • Early Layout Checks 
  • GUI wizard P2P flow

Data Preparation for PathFinder

  • Clamp driven flow
  • Clamp connectivity flow 

Layout Connectivity & Resistance Checks

  • Current Density (CD) Checks
  • Case Studies

Advanced Topics

  • Using Distributed Machine Processing (DMP) for CD checks
  • Large design handling
  • GUI Wizard flow overview
  • Pathfinder Dynamic
  • Driver-Receiver (D2R) flow
  • CECM flow
  • ESD CMM flow
  • Pathfinder-SC overview