Skip to Main Content

Ansys PathFinder
Getting Started

Course Overview

Ansys PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.

Prerequisites

  • Basic understanding of Ansys Totem and ESD concepts expected.

Target Audience 

Chip IP/SoC/CAD Engineers & Designers

Teaching Method

Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops.

Learning Path

Currently, no Learning Path available

Learning Outcome

Following completion of this course, you will be able to:

  • You will gain an understanding of Totem PathFinder layout-based analysis and a proficiency in both running analyses and debugging ESD-related issues using the GUI Wizard-based flow.
  • Understand the basics of Ansys Totem and ESD concepts expected.

 Available Dates

Currently, no training dates available

Learning Options

Training materials for this course are available with an Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.

 

Agenda

This is a 1-day classroom course covering both lectures and workshops. For virtual training, this course is covered over 1 x 2 hour sessions, lectures only.

Virtual Classroom Session 1 / Live Classroom Day 1

  • Module 1 - Introduction to ESD Integrity Verification
  • Module 2 – Early Layout Checks
  • Invoking Totem from Virtuoso (P2P Checks)
  • GUI Wizard Flow
  • Totem GUI Overview
  • Workshop 1
  • P2P Flow
  • Module 3 – Data Preparation and Flows
  • Input files & Modeling
  • ESD Protection devices
  • ESD Rule preparation
  • Commonly used PathFinder flows
  • Module 4 – Resistance Checks
  • Different types of layout connectivity & resistance checks
  • ESD rules for resistance checks
  • Workshop 2
  • Resistance checks w/ Clamp Connectivity flow
  • Debugging layout connectivity issues & resistance violations
  • Module 5 – Current Density Checks
  • Overview & ESD rule preparation for CD checks
  • Workshop 3
  • Current density checks w/ Clamp Connectivity flow
  • Debugging interconnect failure violations
  • Module 6 – Advanced Topics
  • Case studies
  • Using Distributed Machine Processing (DMP) for CD checks
  • GUI Wizard directory setup/customization (for CAD/flow owners)