Power Noise Reliability Sign-off for Custom and Analog IPs with SoC Integration

Mixed-signal, analog, RF and discrete memory devices are increasingly complex, with the shift towards smaller technology nodes and higher levels of integration. Traditional correct-by-construction or Spice-based verifications cannot perform exhaustive layout-based checks that are necessary to ensure these custom design circuits operate properly for voltage drop, noise coupling, and reliability considerations - not only at an IP-level, but also at the SoC-level where they are increasingly utilized.

This presentation will outline ANSYS-Apache’s simulation technologies that address analysis needs for custom and analog IPs including static and dynamic voltage drop, power and signal line EM and ESD integrity sign-off. Additionally, it will demonstrate a full-chip SoC-level analysis flow that can model the noise coupling between high-speed digital and sensitive analog circuits through the silicon substrate, on-die metal power grid, or the shared package planes to help optimize guard ring design.
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