Serial Interconnect Design from Layout to PCIe Specifications

From Dimensions of Electronic Design Seminar, 2012: Post layout validation is a common practice prior to certifying a design. Engineers typically simulate the physical architectures, create electromagnetic-based models, and apply time domain signaling in conjunction with these models. ANSYS has streamlined this process for signal integrity engineers with the use of two products, ANSYS Designer SI and ANSYS SIwave. SIwave with Alinks now embedded, allows users to directly import their layout geometry ready to solve in the SIwave hybrid engine. Critical areas of the geometry can be simulated with additional 3D accuracy by simply identifying the region followed by rigorous ANSYS HFSS analysis. After the physical channel model has been extracted a simple step brings the entire channel into Designer SI. Designer SI, the time domain transient solver is used to simulate time domain channel response driven by transmitter, receiver models such as IBIS or IBIS AMI. User-defined outputs (UDOs) allow the user to quickly view time specification driven measurements such as pass/fail eye characteristics to verify design validity.
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