DDR Compliance

From Dimensions of Electronic Design Seminar, 2012: Predicting today’s memory interfaces is of great importance for many companies that design modern electronics systems. The most common need is an automated and accurate physical extraction of memory channel components and overall system compliance verification of memory interface modules. Using ANSYS SIwave and ANSYS DesignerSI automated capabilities, engineers are enabled to simulate physical behavior of memory channels and verify performance against strict DDR3 electrical standards. ANSYS User Defined Solutions allow calculations and post-processing of raw transient simulation data, which creates User Defined Documents containing detailed information about AC data timing calculations such as setup and hold times, eye diagrams due to the strobe crossing, de-rating including a support for non-ideal voltages for every bit-by-bit falling and rising transition edge.
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