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Design and Analysis of Multi-Die & 3D-IC Systems

The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods, CoWoS (Chip on Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC, provide additional advantages by significantly reducing the interconnect length without any power loss. These new methodologies have introduced innovative ways to handle physics. The complex issues related to the structural, thermal, power, and signal integrity of the entire 3D-IC system cannot be solved using traditional solvers. Advanced simulation methods and highly accurate solvers are required to accurately predict the whole physical coupling in the 3D-IC system.

In this webinar, Jerome discusses the latest developments in 3D-IC design, challenges, and how simulation is the key to successful 3D-IC design. He also presents a comprehensive environment to simulate these physics and achieve the Structural, Thermal, Power, and Signal integrity of the entire 3D-IC system. Chiplets designers, 3D-IC designers, and 3D-IC architects will find this webinar helpful.

What You Will Learn

  • Latest configuration methods like CoWos & Wow
  • Challenges of 3D-IC design
  • Structural and thermal signoff
  • System level analysis

Watch this webinar to understand the challenges, criticality of simulation, and the most effective techniques for successful 3D-IC design.

Jerome Toublanc

Jerome has over 20 years of semiconductor industry experience, working for various EDA companies such as Avanti, Synopsys, and Apache. He has contributed to the successes of worldwide customers in roles ranging from Application Engineer to Product Management and has covered the chip development flow from RTL to GDSII. Jerome is now a Business Development executive for Ansys. He aims to identify emerging multiphysics integrity challenges within the semiconductor industry and develop product solutions for the complete Chip-Package-PCB ecosystem.


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