Join ANSYS at DesignCon 2018 as we celebrate the unveiling of our latest Chip-Package-System (CPS) design flow software — a new, revolutionary standard in automated end-to-end simulation for electronic systems design.
Engineering simulation is the key to ADAS, IoT and 5G
Today's engineers are challenged to design modern electronic systems that operate at higher speeds, with lower power and greater functionality in an ever-shrinking footprint. But with the demand on the rise to design Advanced Driver Assistance Systems (ADAS), IoT, 5G and other high-performance digital systems, electronics designers now require more than just a good circuit simulation tool.
Take your designs to the next level with ANSYS' automated design flow. Now you can perform transient circuit simulation of ECAD and MCAD assemblies directly from a layout for full system verification. Maximize the power efficiency of your devices and accurately predict important electrothermal behavior and electromagnetic coupling within compact designs.
Visit us in booth 747 at DesignCon to learn how ANSYS solves highly complex electronic assemblies and automatically produces transient plots for TDR, eye diagrams and compliance reports. This first-in-the-industry design flow can perform DC analysis, map Joule heating to a mechanical solver, and then produce temperature profiles and associated mechanical deformation and stress maps. It's a chip-package-system solution that allows you to evaluate electrical, thermal and structural behavior, so your design team can optimize system performance prior to building and testing.
Principal Application Engineer
Root-cause Analysis and Resolution of Mobile System Failure through Chip-Package-System Co-simulation
Wednesday, January 31, 1:00 PM
Application Engineer, Electronics Thermal Management, ANSYS Inc.
Wednesday, January 31, 4:00 PM
CTO Signal Integrity Group
Thursday, February 1, 1:00 PM
Sr. Signal Integrity Engineer
Thursday, February 1, 4:00 PM
Visit the ANSYS booth to discover how our newest software capabilities solve core design challenges that speed the development of breakthrough innovations.
Signal-Integrity, Power-Integrity and EMI
Use of an intelligent, integrated, chip-aware design flow process can dramatically streamline the innovation of new and existing electronic devices. ANSYS provides a unique Chip-Package-System (CPS) design flow that leverages advanced modeling and proven simulator technologies to solve complex power integrity, signal integrity, EMI/EMC, ESD and thermal stress challenges.
Learn how the ANSYS automated flows reduce time-consuming manual setup and errors, and streamline the generation of system pass/fail metrics and system verification. The CPS solution integrates IC models with electronic package and printed circuit board simulation. See demonstrations of our enhanced electrical layout focused interface including the ability to include IBIS-AMI models within HFSS layout as well as an advanced chip-package model (CPM) transient circuit simulation and the ability to import native GERBER file formats. Additionally see the ANSYS unique layout assembly capability that supports multiple IC packages, printed circuit boards, and connectors in a single simulation and the new capability of running transient and statistical EYE circuit simulation directly from the layout.
Thermal Efficiency and Mechanical Reliability
Electronic devices today contain many more components within a much smaller form factor than ever before. Even though advances have been made with smaller processor technologies to decrease power draw, the need to predict heat dissipation is now as important as the electrical design itself. More and more layout designs are being done alongside thermal analysis.
See demonstrations of ANSYS Icepak integrated directly into the Electronics Desktop. This advancement delivers electronics cooling analysis directly in the electrical work flow and enhances the user experience. It opens new possibilities for component and system level multi-physics, automation, and robust design. Icepak is in the Electronics Desktop alongside HFSS, Q3D Extractor and Maxwell enabling a smoother overall workflow with robustness for thermal analysis coupled to electromagnetics.
Join ANSYS for the Chip-Package-System Workshop on 3DICs that will cover various topics on power, signal and thermal integrity signoff. Leading industry experts from Xilinx and Samsung Electronics will share relevant case studies on the need for enabling chip, package and system co-design and co-analysis solutions. Don’t miss this exciting opportunity to meet industry experts and learn all about designing robust 3DIC electronics systems for next generation applications.
Root-Cause Analysis and Resolution of Mobile System Failure through Chip-Package-System Co-Simulation
Wednesday, January 31 | 2:50pm - 3:30pm
Byunghyun Lee | Senior Engineer, Samsung Electronics
Woncheol Baek | Senior Engineer, Samsung Electronics
Youngsoo Lee | Senior Product Manager, CPS Solutions, ANSYS
Thursday, February 1 | 2:50pm - 3:30pm
Ling Yang | Design Engineer, Xilinx Inc
KangWei Lai | Director of Engineer, Xilinx Inc
Anusha Prakash | Application Engineer, ANSYS