ANSYS Booth 745
The design of high-speed electronics systems, such as 5G, ADAS, IoT and other wireless and digital systems, is driving high levels of integration, pushing the limits of battery life and continuing to reduce the size of electronic components. For engineers to design within resultant shrinking timing and noise margins in PCBs, electronic packages and complex interconnects, they require a multiphysics engineering environment for simulating and designing entire electronics products. ANSYS simulation technology for chip–package–board design empowers users to evaluate electrical, thermal, and structural behavior before build and test. It enables design teams to optimize systems performance and achieve first-pass design success.
CTO Signal Integrity Group, Samtec
Wednesday, January 29 – 1:00 PM
Production 56 Gbps PAM4 signal channels are already available. Prototype 112 Gbps PAM4 signal channels are currently in development. Routing 112 Gbps PAM4 signals through interconnect poses many technical challenges. In this course, SI expert Scott McMorrow will detail Samtec’s interconnect design process from concept and design through simulation, testing and correlation to high-volume manufacturing. He will explore how the correlation between simulated and measured results builds confidence in the design process.
Sr. Tech Lead/Manager of Power Integrity & Signal Integrity, Intel Corporation
Wednesday, January 29 – 3:00 PM
On both public and private cloud, platform FastPI with Standard chip level PI Model (SPIM) upon Ansys SIwave, facilitates customers’ board level PI design, with quick optimization, review and sign-off for expediting TTM, and with tremendous flexibilities of trade-offs among cost, performance, form factor including stack-up and Z-height, for supporting platform differentiation and product innovation.)
Professor, Graduate School of Science, Technology and Innovation, Kobe University, Japan
Wednesday, January 29 – 4:30 PM
Join this session to learn side-channel passive attacks on cryptographic devices through simulation of AES silicon chip examples. An efficient chip-package-system board (C-P-S) simulation technique will be experienced with established flows to derive full-chip level chip power model (CPM) using commercially available tool chains. The correlation with measurements will be also exemplified.
Senior Director, Application Engineering, ANSYS
Thursday, January 30 – 1:00 PM
In this session, we will cover how ANSYS on-chip electromagnetic solutions can accurately capture all electromagnetic phenomena for mitigating the risk of electromagnetic crosstalk induced performance degradation and failure in high-speed, high frequency and low-power RFICs and SoCs.
Director of Engineering, Bayside Design, Inc. - A Socionext Company
Thursday, January 30 – 3:00 PM
Design of 112Gbps channels present many challenges to today's engineers. The use of High Frequency Structure Simulator (HFSS) is a requirement for solution of full-wave electromagnetic propagation in high speed digital channels. HFSS provides many benefits such as highly accurate channel models, the ability to visualize electromagnetic fields and surface currents, to solve arbitrary structures, and to calculate and visualize radiated fields. This example shows how HFSS was used in the design of a 112Gbps SerDes package and PCB interface, the ability to predict crosstalk, identify the crosstalk mechanism using field visualization, and then eliminate the crosstalk based on these results. The measured vs modelled results are compared against HFSS. We also present the benefits and accuracy of using SIwave with HFSS regions to solve complex 3D regions using HFSS and larger areas of long transmission lines using SIwave in a seamless flow.
Electromagnetic Analysis Specialist, Socionext, Inc
Thursday, January 30 – 4:30 PM
High speed, high density, and miniaturization of chip-package-boards are creating design complexity and long simulation times. In this session, we will introduce Socionext's latest simulation automation and parametric verification process of pre-design interconnect and discuss the future of multi-physics simulation automation.
Visit the ANSYS booth to discover how our newest software capabilities solve core design challenges and speed the development of breakthrough innovations.
ANSYS chip–package–system (CPS) design flow uses advanced modeling and proven simulation technologies to enable an intelligent, integrated, chip-aware system design flow, which solves power integrity, signal integrity, EMI/EMC, ESD and thermal stress challenges. ANSYS will demonstrate our unique layout assembly capability that integrates IC package layout, interposers, connectors, ribbon cables, flex cables and printed circuit board layout — all within a single assembly. This design flow facilitates the emerging CPS design process to support new and existing electronic devices.
Structural and thermal integrity are critical design considerations for packages/PCBs that affect reliability and the product lifecycle. Thermal impact on the package, especially from the IC, is a key driver for material selection, cooling and form factor decisions that ultimately determine the size, weight and cost of the final product. It is, therefore, critical for package and system designers to determine the thermal signature of their system. In our booth, we will demonstrate electromagnetic–thermal coupled analysis and how it can be integrated with ANSYS Mechanical for analysis of the structural impact on the electronic package. We will also highlight our advanced multiphysics capabilities, which deliver unprecedented design insight and ensure design reliability.
More than Moore technologies enabled by the heterogenous integration of multi-dies in 2.5D/3D packaging configurations are economically attractive to realize extreme performance, low latency and high system bandwidth for emerging AI, 5G and automotive applications. However, 2.5D/3D packaging solutions complicate the product design of the chip, package and system due to the cross-coupling of multiphysics effects. Multiphysics challenges — power, signal and thermal integrity, structural reliability and electromagnetic cross-coupling — can have a dire impact on overall product performance. Isolating these effects and examining them separately can adversely impact product performance, design costs and time to market. Learn how ANSYS multiphysics cosimulations for 2.5D/3D-ICs can help you accelerate first-time silicon-to-system success in a fully integrated workflow.
Sponsored sessions are complimentary to DesignCon attendees and exhibitors. Register today to reserve your spot.
Closing Timing in Chip-To-Chip (Chiplet) Based Architectures Using a Hybrid Tool Approach to Generate Appropriate Signal and Power Models
James Church, Broadcom
This presentation will discuss a holistic approach to signal and power integrity for chip-to-chip
||Wed, Jan 29
Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect
Sung-Kyu Lim, Professor, School of Electrical and Computer Engineering, Georgia Institute of Technology
In this talk, we present our latest research accomplishments from circuit design and EDA perspectives
||Wed, Jan 29
De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issues
Anand Raman, Senior Director, ANSYS
In this session we will cover how ANSYS on-chip EM solutions can accurately capture all electromagnetic phenomena for mitigating the risk of electromagnetic crosstalk induced
performance degradation and failure in high-speed, high frequency and low-power RFICs and SoCs.
||Thurs, Jan 30
Reliability Challenges in Advanced Packaging
Craig Hillman, Director, Product Development, ANSYS
This presentation will review the current major material challenges that are influencing reliability discussions in electronics today at various levels of the supply chain, including on-die, packaging, board, and PCBA.
||Thurs, Jan 30
Wednesday, January 29 | 8:00 - 8:45 AM | Ballroom D
Track: 13. Modeling & Analysis of Interconnects, 06. System Co-Design: Modeling, Simulation & Measurement Validation
Wednesday, January 29 | 9:00 – 9:45 AM | Ballroom F
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks
Thursday, January 30 | 3:45 – 5:00 PM | Ballroom D
Track: 14. Machine Learning for Microelectronics, Signaling & System Design