Simulation Software for High-Speed Electronics Design

Production 56 Gbps PAM4 signal channels are already available. Prototype 112 Gbps PAM4 signal channels are currently in development. Routing 112 Gbps PAM4 signals through interconnect poses many technical challenges. In this course, SI expert Scott McMorrow will detail Samtec’s interconnect design process from concept and design through simulation, testing and correlation to high-volume manufacturing. He will explore how the correlation between simulated and measured results builds confidence in the design process.

On both public and private cloud, platform FastPI with Standard chip level PI Model (SPIM) upon Ansys SIwave, facilitates customers’ board level PI design, with quick optimization, review and sign-off for expediting TTM, and with tremendous flexibilities of trade-offs among cost, performance, form factor including stack-up and Z-height, for supporting platform differentiation and product innovation.)

Join this session to learn side-channel passive attacks on cryptographic devices through simulation of AES silicon chip examples. An efficient chip-package-system board (C-P-S) simulation technique will be experienced with established flows to derive full-chip level chip power model (CPM) using commercially available tool chains. The correlation with measurements will be also exemplified.

In this session, we will cover how ANSYS on-chip electromagnetic solutions can accurately capture all electromagnetic phenomena for mitigating the risk of electromagnetic crosstalk induced performance degradation and failure in high-speed, high frequency and low-power RFICs and SoCs.

Design of 112Gbps channels present many challenges to today's engineers. The use of High Frequency Structure Simulator (HFSS) is a requirement for solution of full-wave electromagnetic propagation in high speed digital channels. HFSS provides many benefits such as highly accurate channel models, the ability to visualize electromagnetic fields and surface currents, to solve arbitrary structures, and to calculate and visualize radiated fields. This example shows how HFSS was used in the design of a 112Gbps SerDes package and PCB interface, the ability to predict crosstalk, identify the crosstalk mechanism using field visualization, and then eliminate the crosstalk based on these results. The measured vs modelled results are compared against HFSS. We also present the benefits and accuracy of using SIwave with HFSS regions to solve complex 3D regions using HFSS and larger areas of long transmission lines using SIwave in a seamless flow.

High speed, high density, and miniaturization of chip-package-boards are creating design complexity and long simulation times. In this session, we will introduce Socionext's latest simulation automation and parametric verification process of pre-design interconnect and discuss the future of multi-physics simulation automation.