Simulation Software for High-Speed Electronics Design
ANSYS Booth 745
The design of high-speed electronics systems, such as 5G, ADAS, IoT and other wireless and digital systems, is driving high levels of integration, pushing the limits of battery life and continuing to reduce the size of electronic components. For engineers to design within resultant shrinking timing and noise margins in PCBs, electronic packages and complex interconnects, they require a multiphysics engineering environment for simulating and designing entire electronics products. ANSYS simulation technology for chip–package–board design empowers users to evaluate electrical, thermal, and structural behavior before build and test. It enables design teams to optimize systems performance and achieve first-pass design success.
In-Booth Presentations
Scott McMorrow
CTO Signal Integrity Group, Samtec
Optimizing 112 Gbps PAM4 Interconnect Design Leveraging ANSYS HFSS
Production 56 Gbps PAM4 signal channels are already available. Prototype 112 Gbps PAM4 signal channels are currently in development. Routing 112 Gbps PAM4 signals through interconnect poses many technical challenges. In this course, SI expert Scott McMorrow will detail Samtec’s interconnect design process from concept and design through simulation, testing and correlation to high-volume manufacturing. He will explore how the correlation between simulated and measured results builds confidence in the design process.
Workstations
Visit the ANSYS booth to discover how our newest software capabilities solve core design challenges and speed the development of breakthrough innovations.
Signal Integrity, Power Integrity, EMI
ANSYS chip–package–system (CPS) design flow uses advanced modeling and proven simulation technologies to enable an intelligent, integrated, chip-aware system design flow, which solves power integrity, signal integrity, EMI/EMC, ESD and thermal stress challenges. ANSYS will demonstrate our unique layout assembly capability that integrates IC package layout, interposers, connectors, ribbon cables, flex cables and printed circuit board layout — all within a single assembly. This design flow facilitates the emerging CPS design process to support new and existing electronic devices.
Electronics Reliability
Structural and thermal integrity are critical design considerations for packages/PCBs that affect reliability and the product lifecycle. Thermal impact on the package, especially from the IC, is a key driver for material selection, cooling and form factor decisions that ultimately determine the size, weight and cost of the final product. It is, therefore, critical for package and system designers to determine the thermal signature of their system. In our booth, we will demonstrate electromagnetic–thermal coupled analysis and how it can be integrated with ANSYS Mechanical for analysis of the structural impact on the electronic package. We will also highlight our advanced multiphysics capabilities, which deliver unprecedented design insight and ensure design reliability.
Multiphysics Signoff for 2.5D/3D-ICs
More than Moore technologies enabled by the heterogenous integration of multi-dies in 2.5D/3D packaging configurations are economically attractive to realize extreme performance, low latency and high system bandwidth for emerging AI, 5G and automotive applications. However, 2.5D/3D packaging solutions complicate the product design of the chip, package and system due to the cross-coupling of multiphysics effects. Multiphysics challenges — power, signal and thermal integrity, structural reliability and electromagnetic cross-coupling — can have a dire impact on overall product performance. Isolating these effects and examining them separately can adversely impact product performance, design costs and time to market. Learn how ANSYS multiphysics cosimulations for 2.5D/3D-ICs can help you accelerate first-time silicon-to-system success in a fully integrated workflow.
Technical Presentations
THE HIDDEN CHALLENGES IN 112-GB CHANNEL DESIGN & MODELING
Wednesday, January 29 | 8:00 - 8:45 AM | Ballroom D
Track: 13. Modeling & Analysis of Interconnects, 06. System Co-Design: Modeling, Simulation & Measurement Validation
A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits
Wednesday, January 29 | 9:00 – 9:45 AM | Ballroom F
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks
Panel – Electronic Design Automation Roadmap for Machine Learning and AI Standardization
Thursday, January 30 | 3:45 – 5:00 PM | Ballroom D
Track: 14. Machine Learning for Microelectronics, Signaling & System Design
