DesignCon 2018
Join ANSYS at DesignCon 2018 as we celebrate the unveiling of our latest Chip-Package-System (CPS) design flow software — a new, revolutionary standard in automated end-to-end simulation for electronic systems design.
Engineering simulation is the key to ADAS, IoT and 5G
Today's engineers are challenged to design modern electronic systems that operate at higher speeds, with lower power and greater functionality in an ever-shrinking footprint. But with the demand on the rise to design Advanced Driver Assistance Systems (ADAS), IoT, 5G and other high-performance digital systems, electronics designers now require more than just a good circuit simulation tool.
Take your designs to the next level with ANSYS' automated design flow. Now you can perform transient circuit simulation of ECAD and MCAD assemblies directly from a layout for full system verification. Maximize the power efficiency of your devices and accurately predict important electrothermal behavior and electromagnetic coupling within compact designs.
Visit us in booth 747 at DesignCon to learn how ANSYS solves highly complex electronic assemblies and automatically produces transient plots for TDR, eye diagrams and compliance reports. This first-in-the-industry design flow can perform DC analysis, map Joule heating to a mechanical solver, and then produce temperature profiles and associated mechanical deformation and stress maps. It's a chip-package-system solution that allows you to evaluate electrical, thermal and structural behavior, so your design team can optimize system performance prior to building and testing.
Booth Presentations
Chris Ortiz
Principal Application Engineer
ANSYS Inc.
Root-cause Analysis and Resolution of Mobile System Failure through Chip-Package-System Co-simulation
Individual, separate development environments for chip, package, and board in mobile applications can cause significant system problems. Namely, the respective power noise suppression methods of the components could fail due to interactions of the connected power delivery network (PDN). This presentation demonstrates system failure due to a high voltage ripple caused by a harmonic between a right-shift peak impedance — created by adding decoupling capacitors on a package — and the highest current of a chip at the same frequency. We will demonstrate a cost-effective power noise suppression method that prevents system failure and improves PDN performance.
Wednesday, January 31, 1:00 PM
David Geb
Application Engineer, Electronics Thermal Management, ANSYS Inc.
Integrated Electromagnetic-Thermal Analysis Design Flow
Electromagnetic field simulation enables designers to create innovative electrical and electronic products faster and more cost-effectively. To meet performance needs, advanced communication systems, high-speed electronic devices, electromechanical components and power electronics systems demand increasing power densities, leading to increasing thermal concerns that can be detrimental to product reliability. To accurately assess thermal performance, accurate heat distribution maps must be imported into the thermal tool and accurate temperature fields exported into the electromagnetic tool. Moreover, incorporation of electrical CAD and mechanical CAD (i.e. ECAD and MCAD, respectively) data is needed in the thermal analysis for high fidelity modeling. Additionally, the thermal simulation must simultaneously consider conduction heat transfer in solids, convection heat transfer in fluids (e.g. air and liquid cooling), as well as thermal radiation heat transfer. Traditionally, advanced electromagnetic and thermal simulation tools have been provided in separate software packages and deployed by separate specialized engineering teams. This presentation will present an integrated solution to electromagnetic and thermal simulation and illustrate a design flow that breaks down the traditional barriers between electromagnetic and thermal design teams. This integrated solution gives Electrical and Mechanical/Thermal Engineers a unified platform on which to design and collaborate so that their electrical and electronic products are robust and meet reliability specifications.
Wednesday, January 31, 4:00 PM
Scott McMorrow
CTO Signal Integrity Group
Samtec, Inc.
Trailblazing Past 56G-PAM4 with Samtec Flyover Solutions
As bandwidth requirements rapidly increase, routing signals through lossy PCBs, vias and other components has become one of the most complex challenges designers face. Samtec's “Flyover” design approach breaks the constraints of traditional routing and provides improved signal integrity and architectural flexibility. Leveraging the performance benefits of Samtec’s ultra-low skew Eye Speed® Twinax Cable, Samtec’s Flyover Solutions “fly” critical high-speed signals from the ASIC to the front panel or backplane. This presentation will feature the latest design techniques, component and system modeling, and simulation results based on various ANSYS tools for Samtec’s next-generation Flyover Solution operating at 56G-PAM4 and beyond.
Thursday, February 1, 1:00 PM
Seunghyun Hwang
Sr. Signal Integrity Engineer
Nvidia
Architecting 25Gbps NVLink2.0 Modules with Ansys 3D-Layout
Learn how Nvidia designed the Tesla V100 NVLink interface, which had a significant signal integrity improvement over Tesla P100. Without changing the connector or increasing PCB costs, Nvidia was able to optimize every NVLink trace in the V100 card by leveraging Ansys HFSS 3D Layout. In particular, changes to the GPU ballmap and improvements to the BGA discontinuities are introduced which required hundreds of simulations. Finally, a few interesting SI findings that could only be discovered through post-layout analyses will be shared.
Thursday, February 1, 4:00 PM
Demos
Visit the ANSYS booth to discover how our newest software capabilities solve core design challenges that speed the development of breakthrough innovations.
Signal-Integrity, Power-Integrity and EMI
Use of an intelligent, integrated, chip-aware design flow process can dramatically streamline the innovation of new and existing electronic devices. ANSYS provides a unique Chip-Package-System (CPS) design flow that leverages advanced modeling and proven simulator technologies to solve complex power integrity, signal integrity, EMI/EMC, ESD and thermal stress challenges.
Learn how the ANSYS automated flows reduce time-consuming manual setup and errors, and streamline the generation of system pass/fail metrics and system verification. The CPS solution integrates IC models with electronic package and printed circuit board simulation. See demonstrations of our enhanced electrical layout focused interface including the ability to include IBIS-AMI models within HFSS layout as well as an advanced chip-package model (CPM) transient circuit simulation and the ability to import native GERBER file formats. Additionally see the ANSYS unique layout assembly capability that supports multiple IC packages, printed circuit boards, and connectors in a single simulation and the new capability of running transient and statistical EYE circuit simulation directly from the layout.
Thermal Efficiency and Mechanical Reliability
Electronic devices today contain many more components within a much smaller form factor than ever before. Even though advances have been made with smaller processor technologies to decrease power draw, the need to predict heat dissipation is now as important as the electrical design itself. More and more layout designs are being done alongside thermal analysis.
See demonstrations of ANSYS Icepak integrated directly into the Electronics Desktop. This advancement delivers electronics cooling analysis directly in the electrical work flow and enhances the user experience. It opens new possibilities for component and system level multi-physics, automation, and robust design. Icepak is in the Electronics Desktop alongside HFSS, Q3D Extractor and Maxwell enabling a smoother overall workflow with robustness for thermal analysis coupled to electromagnetics.
Workshop
Join ANSYS for the Chip-Package-System Workshop on 3DICs that will cover various topics on power, signal and thermal integrity signoff. Leading industry experts from Xilinx and Samsung Electronics will share relevant case studies on the need for enabling chip, package and system co-design and co-analysis solutions. Don’t miss this exciting opportunity to meet industry experts and learn all about designing robust 3DIC electronics systems for next generation applications.
Learn More
Customer Presentations
Root-Cause Analysis and Resolution of Mobile System Failure through Chip-Package-System Co-Simulation
A separated development environment among chip, package, and board in a mobile electronics can rather cause a significant system failure by its respective power noise suppression methods due to an interaction of a completely connected PDN(Power Delivery Network). This paper introduces an industry system failure case study due to a drastic voltage ripple caused by a harmonic between a shift-righted peak impedance by added decoupling capacitors on a package and the highest current of a chip at the same frequency. The paper demonstrates how a cost-effective power noise suppression method solves the system failure and improves PDN performance
Wednesday, January 31 | 2:50pm - 3:30pm
Ballroom C
Byunghyun Lee | Senior Engineer, Samsung Electronics
Woncheol Baek | Senior Engineer, Samsung Electronics
Youngsoo Lee | Senior Product Manager, CPS Solutions, ANSYS
Concurrent 3DIC Power Supply Analysis for Xilinx SerDes Interface
Xilinx Virtex Ultrascale+ series product places extremely high requirements on the sensitive analog supply domains. Separate analysis of DIE from interposer and package has caused false alarms and missed noise coupling. Concurrent 3DIC analysis is crucial to meet performance requirements.
When performing power sign off for DIE and interposer separately, each micro-bump on DIE is considered equally effective in providing power to the transistors. So, the problems come in two folds. First is the IR drop. Considering all micro-bumps to be equal supply value eliminates the IR impacts from the interposer. A separate IR analysis on the interposer can be done, the IR value is superimposed to the DIE IR drop, and the summation is regarded as the total IR drop. This makes the results more "equalized', not accurate. Second, the micro-bump has pad current exceeding EM limits. The closest micro-bumps to the current crowded area will provide the most current withdraw, and they may exceed the EM limit. However power ultimately comes from package C4s connected to board to VRM, thus micro-bumps directly underneath the C4 provide lesser impedance paths, and they should consume their fair share. 3DIC concurrent analysis takes into account whole power delivery network without making short cuts, thus they perform more accurate analysis on IR drop and pad current.
Due to resource limitation, separate supply domains on DIE need to be merged on the package. DIE-only analysis won't reveal the coupling impact from merged package. Package-only analysis won't provide transistor level accuracy simulations. Concurrent analysis provides transistor level accurate power supply waveforms, thus can be applied as guideline for power delivery network. 3DIC concurrent power analysis is key to ensure design quality and guarantee performance in a demanding 32G+ environment.
When performing power sign off for DIE and interposer separately, each micro-bump on DIE is considered equally effective in providing power to the transistors. So, the problems come in two folds. First is the IR drop. Considering all micro-bumps to be equal supply value eliminates the IR impacts from the interposer. A separate IR analysis on the interposer can be done, the IR value is superimposed to the DIE IR drop, and the summation is regarded as the total IR drop. This makes the results more "equalized', not accurate. Second, the micro-bump has pad current exceeding EM limits. The closest micro-bumps to the current crowded area will provide the most current withdraw, and they may exceed the EM limit. However power ultimately comes from package C4s connected to board to VRM, thus micro-bumps directly underneath the C4 provide lesser impedance paths, and they should consume their fair share. 3DIC concurrent analysis takes into account whole power delivery network without making short cuts, thus they perform more accurate analysis on IR drop and pad current.
Due to resource limitation, separate supply domains on DIE need to be merged on the package. DIE-only analysis won't reveal the coupling impact from merged package. Package-only analysis won't provide transistor level accuracy simulations. Concurrent analysis provides transistor level accurate power supply waveforms, thus can be applied as guideline for power delivery network. 3DIC concurrent power analysis is key to ensure design quality and guarantee performance in a demanding 32G+ environment.
Thursday, February 1 | 2:50pm - 3:30pm
Ballroom F
Ling Yang | Design Engineer, Xilinx Inc
KangWei Lai | Director of Engineer, Xilinx Inc
Anusha Prakash | Application Engineer, ANSYS
