As designs increase in complexity to cater to the insatiable need for more compute power spurred by different AI applications ranging from data centers to self-driving cars, designers are constantly faced with the challenge of meeting the elusive PPA (Power Performance and Area) targets.
PPA over-design has repercussions resulting in increased product cost as well as potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance which result in higher power density. Traditional approaches of uniformly over-designing the power grid which has worked in the past is no longer an option with routing resources becoming severely constrained. To add to these woes, there are hundreds of combinations of PVT corners to solve for along with the increasing number of applications.
For example, an ADAS SoC is used for a variety of applications such as pedestrian detection, parking assist, vehicle exit assist, night vision, blind spot monitoring, collision avoidance, and a whole lot more. The numbers of vectors designers need to run simulations for have increased multi-fold. It is nearly impossible to uncover potential design weaknesses when you are simulating only a handful of vectors for just a fraction of second. How do you ensure you have enough design coverage?
Power grid design has become a limiting factor for achieving the desired performance and area targets in next generation SoCs. Sharper slew rates, higher current densities and faster switching speeds pose significant challenges to power integrity and reliability signoff. Lower operating voltages lead to tighter noise margins, resulting in a chip that is very sensitive to changes in supply voltage. Higher device density and longer wires in these advanced designs lead to increased node count by at least an order of magnitude posing significant capacity and performance challenges for traditional EDA tools to address.
As the design size increases, the turnaround time for solving billion-plus instance designs becomes very critical. Next generation SoC power integrity and reliability signoff solution should scale elastically with capacity and performance. It is imperative to iterate designs over multiple operating conditions and scenarios rapidly, with an overnight turnaround time to maximize design coverage. Also, it is equally important to gain key insights from these large design databases to prioritize design fixes.
In this on-demand webinar, learn how NVIDIA has developed a workflow to run a flat, full-chip power integrity and reliability signoff analysis using a fully distributed compute and big data solution with ANSYS RedHawk-SC. They achieved a turn-around time of well under 24 hours for full-chip flat power signoff analysis on NVIDIA’s largest GPU – Volta, which contains around 21 billion transistors.
Additionally, silicon correlation exercises performed on the Volta chip using RedHawk-SC produced simulated voltage values that were within 10 percent of silicon measurement results. Discover how NVIDIA’s most powerful GPU uses ANSYS’ next generation SoC power signoff solution based on big data to deliver the best performance for cutting-edge AI and machine learning applications.
