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Multiphysics Simulations Help IC Design Engineers Achieve 7nm FinFET Success

As electronic devices become smaller and more powerful, engineers will need to account for variability to ensure product performance.

In the good old days of integrated circuit (IC) design, engineers could use a siloed approach to sign off on a chip’s power integrity, thermal reliability and logic path timing consistency. However, this technique isn’t an effective way to design 7nm fin field effect transistors (FinFETs).

These margin-based techniques test if an IC design can survive a series of siloed scenarios. These scenarios cycle through the worst-case conditions for one signoff (say power integrity) and nominal conditions for all other signoffs (in this case thermal reliability and logic path timing).

However, when engineers design 7nm FinFETs, the siloed methodology is unable to determine how the cross coupling of multiphysics effects impact timing signoff, power integrity and thermal reliability.

For instance, the silicon performance of low-power devices at the 7nm scale will be impacted by voltage drop fluctuations and process variations. Traditionally, margin-based techniques worked because variability has a small effect in a larger space. But at 7nm, variability can range from 30 to 40 percent.

As many engineers are used to margining variability issues, they may not be prepared when these issues impact the operating frequency of silicon in smaller devices. With the use of ANSYS multiphysics simulations, engineers can address variabilities in power integrity, thermal reliability and logic path timing consistency to produce an optimal 7nm FinFET design.

Optimize a FinFET Design without Margin-Based Methodologies or Monte Carlo SPICE Analysis

A silicon wafer with processor cores

Due to variations in the temperature, voltage and power supply, every FinFET will experience a unique local environment. Additionally, as FinFET devices age, new sources of variability will need to be considered.

As a result, disparate local environments and silicon aging need to be accounted for when designing FinFETs for critical systems within autonomous vehicles, medical devices and 5G communications.

Since IC design teams are no longer able to marginalize variability, they must use tools like simulation to measure it.

One method of measuring variability is running a Monte Carlo analysis using a simulation program with integrated circuit emphasis (SPICE). However, these Monte Carlo SPICE analysis tools are time-consuming, computationally expensive and unable to handle variabilities with non-first-order effects.

Using ANSYS multiphysics simulations, engineers can quickly model interdependent variation effects in order to assess the life and performance of FinFETs.

ANSYS Path FX and ANSYS RedHawk-SC Optimize FinFET Designs

IC design teams can use ANSYS Path FX software to replace Monte Carlo SPICE analysis. Path FX is a SPICE-accurate, logic path timing solution that can be used to simulate high sigma process variations and supply noise.

The impact of dynamic voltage drops on circuit performance

Path FX complements timing signoff workflows and leverages transistor-level models to simulate every device and all nonlinearity within a design.

The Path FX software can also account for the power and ground noise of each FinFET in the design by including the supply voltage waveforms in the simulation. The tool can even take temperature and silicon aging into consideration when performing simulations.

IC design teams can use ANSYS RedHawk-SC to simulate supply voltage variations and then plug the results into Path FX to determine process variations. This enables the team to assess the impact of dynamic voltage drop on logic path timing. This assessment is critical to achieve the target maximum frequency on silicon and optimize the functional yield of FinFET designs.

To learn of more ways IC design teams can link RedHawk-SC to Path FX, read the white paper: Timing Is of the Essence: Variability-aware and SPICE-accurate Timing Closure. Or, watch the webinar: Addressing Multiphysics Challenges in 7nm FinFET Designs.