Every year cellphones get more powerful, yet batteries barely see improvement. As a result, cellphone designers are tasked to meet next year’s performance demands on last year’s power supply.
This challenge is forcing manufactures to beef up cellphone hardware, with upgraded multicore central processing units (CPU), graphical processing units (GPU) and screens, expanded memory and other subsystems.
Each upgrade eats power faster and the power drain only increases as the user multitasks. Without improving battery performance or finding power savings in the design of the hardware, the resulting power gap will reduce the battery life and thermal performance of the phone.
Simulation tools are essential for designing low-power solutions for mobile phone design. Engineers gain the ability to recognize, address and reduce the power gap earlier in the design process. The sooner engineers discover power gaps, the sooner they can address them.
The Advantage of Addressing Power Early
Product release schedules and design costs are severely impacted when issues are uncovered late in the development cycle. Therefore, if engineers make power-related decisions early — for example, in the architecture phase — they have a better chance of maximizing power savings.
Higher-level abstractions, such as register-transfer level (RTL), describe the design at the functional level. RTL power analysis gives engineers the ability to uncover opportunities for high-impact changes early in design. This is preferable to finding issues post-synthesis, where the design is decomposed into a sea of gates. However, engineers often raise a key concern about the accuracy of RTL power estimation when compared to gate-level power.
Fortunately, front-end power solutions can bridge the gap between RTL power and gate-level power by accounting for physical effects, such as clocks and wire capacitance. These solutions deliver results 20- times faster than traditional gate-level methodologies, so designers can identify and make power decisions early and reliably.
Designing Mobiles for Power Efficiency
Advanced mobile processors leverage sub-16 nm fin field-effect transistor (FinFET) process technologies to pack more functionality and performance into the device at low power. However, this increases the transistor density resulting in an increased power density. This growing power density will contribute to mounting power and thermal concerns.
Engineers need to deliver greater functionality at lower power. To do this, they need to ensure the RTL is designed to be power-efficient. When engineers uncover power reduction opportunities early, they can obtain huge power savings as high as 70 percent. Engineers achieve this power saving using:
- Hierarchical clock gating through RTL techniques.
- Powerful interactive debugging.
- Power-efficiency metrics.
ANSYS PowerArtist can be used to identify these power optimization opportunities early. In fact, Qualcomm leveraged RTL power analysis methodologies when optimizing the design of their Adreno GPU to achieve superior power efficiency.
Watch this webinar to learn how Qualcomm optimized power in their mobile GPUs.