A Methodology for Comprehensive and Productive Power Noise and Reliability Closure for Advanced SoC Designs - White Paper


One of the key technology trends driving the semiconductor industry is the adoption of FinFET processes. As opposed to a traditional planar transistor, the FinFET has an elevated channel or 'fin', which the gate wraps around. Due to their structure, FinFETs consume much lower leakage power and allow greater device density. Compared to planar transistors, FinFETs operate at a lower voltage and offer higher drive current. All of these properties lead to lower circuit delay, lower leakage and higher performance packed into a smaller area. This also means that FinFETs offer reduced cost per unit performance. Designing a complex SoC using advanced FinFET-based technologies for first pass silicon success requires proven tools and methodology.


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