Best Practices on Mitigating the Challenges of Power Noise Closure for Analog and IP Designs and a Foundry Case - Webinar

Analog and IP designs require optimal power noise closure for top performance. Your best practices workflow should include ANSYS Totem, especially for advanced FinFET technologies.

Learn how ANSYS Totem can provide power/noise and reliability analysis from the early design stage to sign-off for analog/mixed-signal IP. Discover how Totem can help you with advanced debugging and exploration of design weakness, as well as advanced analysis for FinFET technology nodes.

In addition, KK Lin, Director of Foundry Marketing for Samsung Foundry, will present a case study on foundry qualification of ANSYS products, including Totem for FinFET technology and accuracy correlation analysis.
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