De-Risking High-Speed Serial Links from On-Chip Electromagnetic Crosstalk and Power Distribution Issues
High speed/frequency RF transceivers and SoCs for 5G, mobile, AI, automotive and networking applications are becoming increasingly susceptible to electromagnetic (EM) cross coupling effects. Learn how ANSYS on-chip EM solutions can accurately capture all electromagnetic phenomena for mitigating the risk of electromagnetic crosstalk-induced performance degradation and failure in high-speed, high-frequency and low-power RFICs and SoCs. See how NVIDIA applies ANSYS EM tools to address high-speed serial link design challenges that come with denser routings and aggressive floorplans, including on-chip EM crosstalk and large di/dt induced supply noise.
Dai Dai, Mixed Signal Design Manager, NVIDIA
Dai Dai received his B.S. degree from Tsinghua University, Beijing, China in 2010 and M.S. degree from the University of California, Los Angeles, in 2012, both in electrical engineering. He has been with Nvidia since 2013, where he is currently a Mixed-Signal Design Manager with the high-speed wireline team. His research interests include high-speed serial I/O transceiver designs, PLLs and data converters.
Yorgos Koutsoyannopoulos, Vice President, Engineering, ANSYS
Experienced Chief Executive Officer with a demonstrated history in the EDA and semiconductor industry. Strong business development professional skilled in entrepreneurship, enterprise software sales, EDA, semiconductors, management, startups and international transactions.