An Automated Method for Using FEA to Identify PTHs and Microvias at Failure Risk
Plated through-holes (PTHs) and vias are widely deployed across the electronics industry for their ability to interconnect signal circuits at different printed circuit board (PCB) layers. But for many designers and engineers, vias and PTHs are sources of concern and difficulty when it comes to reliability: They are frequently the cause of open circuits on PCBs. Traditionally, the inconsistency of plating quality across manufacturers and the lack of robust material characterization make it challenging to develop models capable of predicting the reliability and manufacturability of these interconnects.
In this webinar, we will discuss the reliability challenges inherent in the utilization of PTHs and microvias. You will learn a methodology to analyze tens of thousands of interconnects on a PCB — and identify which are likely to fail — by simulating them under thermal loading using fine element modeling (FEM) and performing manufacturability and reliability analyses.