Achieve Faster IC Power Closure Using Streamlined Chip–Package Co-Analysis - Webinar

As system-on-a-chips (SoCs) grow in density and complexity, the variations in switching current and parasitic profiles increases. This requires power integrity engineers to focus on local details to ensure accurate power delivery. This focus drives the need for granular resolution of C4 bump-level connections between the SoC and the package. RedHawk-CPA provides a comprehensive power-analysis solution using chip and package layouts that allow for “what-if” analysis so you can view the impact to the overall power delivery when changes are made to the layout. This webinar introduces you to chip–package analysis using RedHawk-CPA. It illustrates how RedHawk-CPA and its unified environment perform DC, transient and AC power-integrity analysis using chip and flip-chip package layouts to improve the level of accuracy and shorten time to power closure.
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