Design-For-Reliability Flow in 7nm Products with Data Center and Automotive Applications


In this presentation, Dr Jae-Gyung Ahn describes Xilinx’s improved Design-For-Reliability (DFR) flow in the 7nm process technology node for data center and automotive applications. Topics include thermal issues that are estimated in the design stage to meet the reliability target for high power applications. Also discussed are Xilinx’s methodology to estimate the Middle-End-Of-Line (MEOL)/Back-End-Of-Line (BEOL) length of the whole chip, with voltage information to guarantee the reliability of extremely large chips, the impact of package components on product reliability, and aging simulations that must be considered more carefully for automotive applications.


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