Increasing IP integration causes high current demand on supply networks; impacting IP operating voltage and resulting in chip performance degradation. In highly integrated SoCs, IP validation for power, noise, and reliability is imperative for first time silicon success.
Apache enables IP analysis, with transistor-level accuracy, across multiple operating modes, and without compromising run-time performance. Apache's innovative modeling technology captures the IP's power and electrical signature with the ability to control granularity and visibility. Apache enables integration of multiple IP and predicts the impact of global and local power noise through substrate and power networks across chip, package and PCB.