Keeping Up with Moore’s Law
From Dimensions of Electronic Design Seminar, 2012:
Today’s mobile electronics demand tighter power budgets while delivering greater functionality and performance. Advancements in semiconductor technology aim to address these conflicting design targets. However, as chips migrate to sub-20nm process nodes or use stacked-die (3D-IC) technologies, the ability to model and accurately predict the power/ground noise and its impact on the IC’s performance and reliability become critical for success with advanced low-power designs.
This track discusses tools and methodologies that address power and reliability challenges, along with real designer experiences:
- Comprehensive RTL2Gate methodology with PowerArtist‘s market-leading RTL design-for-power solutions and RedHawk’s industry-standard platform for dynamic power sign-off
- The latest generation of RedHawk architected for stacked-die/3D-IC design analysis with hierarchical dynamic simulation and multi-pane/multi-canvas GUI
- Tools for addressing power noise reliability challenges, such as electromigration (EM) and electrostatic discharge (ESD), specifically at sub-20nm process nodes