Active Power Noise Modeling Toward Design for EMI Compliance of IC Chips - Conference Paper

Design of digital IC chips for electromagnetic interference (EMI) is enabled for electromagnetic compatibility (EMC) conscious applications. Chip-package-system board (C-P-S) integrated power noise simulation uses passive and active CPMs for an IC chip with different number of active digital circuits (with different design sizes). The chip was designed and fabricated in a 65 nm CMOS technology, and additionally embedded on-chip power noise monitors. The power noise waveforms exhibit quantitative consistency among the C-P-S simulation with a full-chip Si substrate network model and on-chip power noise measurements with 100 psec and 100 uV resolutions.