Put a Cap on DDR System Power Supply Noise - Article - ANSYS Advantage - V12 I3

Smart connected products require more functionality in smaller multivariant packages. As the global power budget is reduced and the operating frequencies required to deliver rich features increase, engineers are confronting the issue of power supply noise. The chips, packages and printed circuit board all contribute to power supply noise, so the complete system must be optimized to limit noise across the voltage and ground terminals of the transistors for error-free performance. STMicroelectronics engineers used ANSYS tools to identify and correct a power integrity problem in the complex design of a DDR system that might have otherwise delayed the product launch.


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