Power Retooling for Chips - Article - ANSYS Advantage - V10 I3

In a conventional approach, chip power-consumption analysis begins late in the design flow and occurs typically when the physical design is complete. At this stage, possible changes that can impact power are limited by schedule and cost considerations. AMD used ANSYS PowerArtist to apply a design-for-power approach at an early stage in the design flow, making it possible to reduce power consumption to unprecedented levels.