Package and Board Power Integrity Design with ANSYS SIwave-PI - Application Brief

Modern design challenges such as 3-D-IC and 2.5-D silicon interposers are excellent examples of how we pack more transistors into a smaller form factor. This is also evident from the trends requiring chip-aware system design with increasing transistor density and higherthroughput on device IO interfaces. Smaller gate size requires a reduction in gate voltage, thereby shrinking power noise margins. It’s a huge challenge to stay within the shrinking voltage noise limits and keep pace with increasing current demand, since engineers also have to account for signal transitions occurring due to faster edge rates and more transistors switching simultaneously. Typically, to address these issues, design engineers have to reduce the power delivery network (PDN) impedance. In redesigning PDNs, problems become even more complex, as the required PDN impedance reduces to the order of milliohms and, in some cases, microohms. An effi cient power integrity tool is required.
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