Design for reliability is a key consideration for the successful signoff of next-generation FinFET system-on-chip (SoC) applications including autonomous vehicles, advanced driver assistance systems, 5G communication electronics, mobile and high-performance computing. Ansys provides comprehensive workflows with foundry-certified accuracy for multiphysics simulations across chips, packages and systems that capture the various failure mechanisms and provide signoff confidence for first-time silicon success.
Join us for this free webinar which provides a detailed analysis of Ansys’ multiphysics reliability signoff solution for next-generation FinFET SOCs.
Learn how Ansys addresses multiphysics reliability signoff challenges for advanced FinFET SoCs.
Discover how Ansys chip-package-system reliability signoff solutions address thermal, thermal-aware electromigration, failure in time and electrostatic discharge to create robust and reliable electronics systems.
Receive expert tips on using Ansys comprehensive workflows to capture failure mechanisms and deliver signoff confidence.
Anant Narain currently serves as a senior area technical manager for Ansys, specializing in the optimization of power, power noise and reliability analyses for chips, packages and systems. He joined Ansys in 2007 and supports the field application engineering team. Prior to joining Ansys, Anant worked in academia as assistant professor at National Institute of Technology, Allahabad, supporting very large- scale integration (VLSI) design and CAD of VLSI areas.