“The integrated electronic-photonic workflow provided by Ansys to co-design and co-simulate Silicon Photonics and CMOS chips is an indispensable tool to speed up our design process and results in better chips with fewer errors and a shorter time to market.”
- Jinsung Youn Research Scientist / Large-Scale Integrated Photonics / Hewlett Packard Labs
Dense wavelength division multiplexing (DWDM) Silicon Photonics (SiPh) is one of the technologies that we are working on. To design a ring-resonator-based co-packaged (see image 1) DWDM SiPh chip, it was important to implement a comprehensive and robust design flow with the flexibility to efficiently uncover the best designs while eliminating the need of re-spin. That meant we had to account for process and temperature variations, capture the complex interplay of multiphysics effects, and optimize the combined optical and electrical performance of the design.
The optical and electrical blocks in SiPh transceivers have traditionally been modeled in separate design environments and by dedicated domain solvers in a disjointed workflow. It is possible to manually capture the electrical-to-optical and optical-to-electrical behaviors when moving between the electrical and the optical circuit simulators, but this patchy workaround is cumbersome, prone to errors, and simply doesn’t scale. The 3D assembly of co-packaged optics brings even tighter integration and multiphysics complexities that, if not considered, can lead to product failure. Additionally, non-idealities from process and temperature variations can result in undesirable shifting of the micro-ring resonances. This all makes it very challenging to accurately predict both the frequency and time domain performance of such a complex design in a realistic way.