Hewlett Packard Labs Speeds Up Design Process

“The integrated electronic-photonic workflow provided by Ansys to co-design  and co-simulate Silicon Photonics and CMOS chips is an indispensable tool to speed up our design process and results in better chips with fewer errors and  a shorter time to market.”

- Jinsung Youn  Research Scientist / Large-Scale Integrated Photonics  / Hewlett Packard Labs

Introduction

Dense wavelength division multiplexing (DWDM) Silicon Photonics (SiPh) is one of the technologies that we are working on. To design a ring-resonator-based co-packaged (see image 1) DWDM SiPh chip, it was important to implement a comprehensive and robust design flow with the flexibility to efficiently uncover the best designs while eliminating the need of re-spin. That meant we had to account for process and temperature variations, capture the complex interplay of multiphysics effects, and optimize the combined optical and electrical performance of the design.

Challenges

The optical and electrical blocks in SiPh transceivers have traditionally been modeled in separate design environments and by dedicated domain solvers in a disjointed workflow. It is possible to manually capture the electrical-to-optical and optical-to-electrical behaviors when moving between the electrical and the optical circuit simulators, but this patchy workaround is cumbersome, prone to errors, and simply doesn’t scale. The 3D assembly of co-packaged optics brings even tighter integration and multiphysics complexities that, if not considered, can lead to product failure. Additionally, non-idealities from process and temperature variations can result in undesirable shifting of the micro-ring resonances. This all makes it very challenging to accurately predict both the frequency and time domain performance of such a complex design in a realistic way.

Engineering Solution

• The Ansys Lumerical and Cadence joint electronic-photonic co-simulation was used to capture both the electrical and optical sub-circuitries in a single design  environment; the electrical, optical, and electro-optical behaviors were simulated.
• Ansys Lumerical CML Compiler was used to generate a SiPh process design kit  (PDK) based on simulation and measurement data. The electronic circuits were  designed with a CMOS foundry PDK.
• The interposers and packages were analyzed by a full-wave electromagnetic (EM)  solver from Ansys Electronics Desktop (AEDT).  For signal and power integrity, the insertion and reflection losses and IR drop were evaluated. Thermal simulations  were done using Ansys Icepak to extract the temperature map of the SiPh  interposer and analyze its impact on the ring resonator’s performance.

Benefits

• The seamless co-design environment improved our efficiency and significantly  reduced the chances of errors compared to other disjointed solutions in the  market. 
• The co-simulation workflow enabled full optical spectrum, optical eye diagram,  and electrical eye diagram analysis.
• The use of Ansys Lumerical’s INTERCONNECT solver and Ansys OptiSLang  accurately predicted the ring resonator’s optimal Q-factor and bias voltage to  satisfy our bit-error rate specifications.
• Thanks to the multiphysics workflows between Ansys Lumerical and the Ansys  Electronics solution suite, we could accurately predict the impact of thermal  variations on the resonance wavelength of the micro-rings and calculate how  much power would be needed for thermal tuning.
• We can confidently say that thanks to the exceptional support of the Ansys multiphysics and photonic simulation solutions and teams, we can fully verify  and optimize DWDM SiPh circuits.