What is Crosstalk: Electromagnetic Challenges and Trends in Electronics

The EM signals causing the interference are known as the aggressors while the EM signal affected by crosstalk is known as the victim.

Crosstalk occurs via two mechanisms:

1. Capacitive crosstalk caused by the electrical field
2. Inductive crosstalk caused by the magnetic field

Engineers developing system-on-chip (SoC) architectures that ignore crosstalk are taking a big risk. Crosstalk can produce electronic design errors that could lead to delays in reaching the market and cost overruns.

The Challenges of Identifying EM Crosstalk

EM crosstalk is more challenging. First, the symptoms of the problem do not appear in one metric — like timing failure. Instead, crosstalk often manifests as a degradation in some key performance criterion that varies from design to design. Therefore, identifying the issue as crosstalk is the first challenge.

To make matters more complex, crosstalk usually involves unwanted coupling between digital, analog and radio frequency (RF) blocks. Either one can be the aggressor or victim.

EM crosstalk needs to be identified, debugged and resolved differently in different designs. Traditional solutions involve architecture or software tricks that prevent the modes of operation that trigger the problem. However, this is becoming financially and technically untenable as designs have grown in complexity and speed.
 

The Challenges of Modeling EM Crosstalk

Most of these structures have complex physical layouts that require a large mesh to simulate the resistance, capacitance, inductance, coupling capacitance and mutual inductance.

A second modeling factor that increases the size of crosstalk models is that engineers can’t analyze EM crosstalk by limiting the focus to a small bounding box within the design. Analyzing neighborhood victim signals works well when assessing electrical capacitive coupling. However, magnetic fields can travel along large loops, form outside the immediate neighborhood of a victim signal or encircle the whole layout of the chip.

Additionally, it’s hard to limit the size of a model generated by EM crosstalk tools because it needs to include all the nets that contribute to the crosstalk problem and all the nets and structures that might have an impact on the performance of the circuit.

To be useful downstream in development, the crosstalk model must:

1. Quickly compute in a simulation program with integrated circuit emphasis (SPICE)
2. Operate in various nonlinear and noise simulations within a SPICE environment
3. Exist in a database that crosses the boundaries of blocks or silicon dies

These three requirements are hard to meet given the typical size and complexity of crosstalk models.
 

The Emerging Need for EM Crosstalk Analysis in SoCs

EM crosstalk is a big concern for engineers because of the demand for electronic systems to increase in bandwidth and decrease in size. This puts high-speed circuitry and high-bandwidth channels in proximity.

As electronics become smaller, crosstalk will become a bigger problem. 

Additionally, the continuous increase in internal clock frequencies (5 to 10 GHz) and the increase in data rates (above 10 Gbps) are also fueling the emergence of crosstalk issues.

In short, fast speeds and small electronics create crosstalk; consumer demands are creating SoC trends that make it impossible to ignore parasitic inductance and inductive coupling.
 

SoC Architecture that Is Prone to Crosstalk

Those who target on-chip clock frequencies of 25 GHz, however, will have to think about how to safely model the 3rd harmonic, which falls into microwave frequencies.

EM crosstalk can affect signal magnitudes, or noise level. Hence, the impact of crosstalk is further exacerbated by the decrease in signal voltage levels and the increase in sensitivity to noise driven by lower-power trends in SoC applications.

Ethernet, fiber channel and peripheral component interconnects (PCI) can also be sources of crosstalk. To achieve high data rates, these buses employ multiple serial lanes that operate in parallel. For example, a 100 Gbps ethernet can employ 10 channels that are each running at 10 Gbps. When so many high-speed serial lanes reside in a single system, every lane can be a potential aggressor or a potential victim — a true crosstalk nightmare.

Other architectural trends that increase the likelihood of EM crosstalk include:

• High-speed analog blocks on one SoC
  • Like phase-locked loops (PLLs) and voltage-controlled oscillator (VCO)
• Multiple high-speed clock networks on the same chip
  • Clocks don’t need to operate at high frequencies — victim clocks running at 10 GHz can be affected by aggressor clocks running at 2 GHz.
• RF or high-speed analog blocks adjacent to high-speed digital blocks
  • Shared ground nets and silicon substrates can’t be tapped as a ground.
  • Silicon substrate remains a key noise-propagation channel between blocks.
• Seal rings and scribe lines inserted by foundries
• Low power designs with small signal-to-noise margins
• Sensitive control/reset signals that can be set by crosstalk glitches
• Integrated fan-out wafer-level packaging techniques
  • Multiple dies in proximity increase the likelihood of EM crosstalk.
     

Not All EDA Tools Can Model Crosstalk

With the advent of advanced technologies and SoC architectures, ignoring electromagnetic crosstalk is risky.

Learn how to use Ansys Pharos to identify and alleviate crosstalk.

To learn more about crosstalk, read the article: Optimize High-Speed Serial Links for Crosstalk.