Full-chip ESD Integrity Analysis
ANSYS PathFinder is a planning, verification and sign-off solution targeting electrostatic discharge (ESD) robustness and integrity for IP and full-chip SoC designs. The analysis is performed at the layout and circuit-levels to identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events. It is certified by a number of foundries to perform accurate interconnect parasitic extraction, ESD simulation, and electromigration (EM) or current-density rule handling.
Industry surveys indicate that up to 35 percent of integrated circuit (IC) field failures are ESD related. The convergence of advanced process technology, increasing levels of digital and analog integration, higher operating frequencies, proliferation of handheld devices, and advanced package designs with tighter pitch and fewer layers exacerbate the impact of ESD-induced failures in integrated circuits.
Using full-chip-level modeling techniques, ANSYS PathFinder can determine if a design meets ESD guidelines; it can identify weak areas of the design (layout or circuit) that are most vulnerable. The software performs early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. PathFinder can model an ESD event and analyze the design to predict which clamp cells will be effective and which cells will not.