ANSYS PathFinder

ANSYS PathFinder

Electrostatic discharge integrity: IP to SoC

ANSYS PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.

PathFinder provides:

Coverage
Using layout and circuit-level analysis you can identify and isolate design issues that can cause chip or IP failure due to charged-device model (CDM), human body model (HBM) or other ESD events.

Foundry Certification
PathFinder is certified by a number of foundries as an ESD sign-off solution, giving you the assurance that the interconnect parasitic extraction, HBM/CDM ESD simulation and current-density checks on ESD discharge paths are accurate by foundry standards.

Root Cause Detection
PathFinder offers layout-based analysis and a GUI for detecting layout issues that could lead to ESD events.

Capabilities

HBM/CDM ESD Events

PathFinder provides you with comprehensive coverage of on-chip ESD events, which is a requirement for most chip designs.

HBM/CDM ESD Events
Silicon-Correlated Accuracy

Increasing current densities in advanced technologies lead to more ESD issues. PathFinder provides accurate ESD analysis prior to sign-off to ensure first-time silicon success.

Silicon-Correlated Accuracy
Layout-Based Analysis and Root Cause Detection

RedHawk offers you the capacity and performance to simulate designs having over 1 billion instances using advanced Distributed Machine Processing (DMP) techniques.

Capacity and Performance
Single Pass Simulation and Results Analysis

PathFinder’s integrated data modeling, extraction and simulation engine offer you an end-to end-solution for ESD verification.

Single Pass Simulation and Results Analysis
Capacity and Performance

With distributed computing, PathFinder can simultaneously handle hundreds of domains in one analysis for faster turnaround.

Capability and Performance
Library to SoC-Level ESD Integrity

PathFinder offers you the coverage, accuracy, capacity and performance to address ESD issues from standard cell to SoC levels of design.

Library to SoC-Level ESD Integrity

See how our customers are using our software:

ANSYS PathFinder Efficient OnChip ESD

Renesas

In advanced process technologies, as the number of power domains and metal layers increase, ESD issues grow. See how Renesas is able to effectively address ESD issues using ANSYS PathFinder. View Case Study