Semiconductors: New in ANSYS 19
Make critical design choices with confidence using ANSYS 19. Design for performance of electronics systems by simultaneously optimizing various design attributes such as power noise, thermal properties and reliability across the chip, package and system (CPS). Reduce your simulation time from days to a few hours with the ANSYS RedHawk-SC big data platform and prioritize design fixes with its actionable analytics. Design for reliability with ANSYS Totem and ANSYS RedHawk chip-package thermal co-analysis solutions, which support advanced FinFET technology nodes (N7 and below) across all major foundries. Analyze milliseconds of application scenarios faster — by orders of magnitude — with ANSYS PowerArtist RTL power profiling. Identify critical power hotspots and cycles early in the design flow for the robust power and thermal design of the chip, package and system.
Multiphysics signoff for chip, package and system
Traditional, margin-driven and silo-based design approaches to the chip, package and board severely limit your ability to optimize these systems globally— without overdesigning. The chip model analyzer in ANSYS 19 enables you to create a full, power delivery network (PDN) current model across the wide frequency spectrum of the chip, package and board. The full PDN current profile helps in simulating large current transients — from a few milliseconds to seconds in duration — in the chip, package and board boundaries that lead to catastrophic, global rail voltage collapse.
Chip, package and board co-simulation and co-analysis are critical in optimizing product performance, and in helping you make cost-efficient choices regarding the number of decoupling capacitors and the type of package selection. Real application vectors from emulators can be profiled for power using PowerArtist to create pseudo-current profiles for the full- chip PDN without any physical design. These current profiles will match the power envelope of the real vectors from the emulator to enable early power and thermal analysis of the chip, package and board. This is vital early in design exploration to help you confidently select the right package.
Design for low power
Mobile devices are power-source limited, while high-end servers are thermally limited. Greater functional integration and the higher switching speed of FinFET devices have increased the dynamic power consumed by the chip and has widened the “power gap” — the difference between the amount of power a battery can supply and the amount of power required for reliable operation of the devices. This causes reduced battery life and degraded thermal performance, and makes designing for low power a critical need.
PowerArtist in ANSYS 19 helps designers address power early in the register-transfer level (RTL) design phase to create power-efficient products for next-generation applications. PowerArtist provides 7nm-proven RTL power accuracy within 15 percent of gate-level power, by modeling the physical effects of clock tree, wire capacitance and multibit flops. Turnaround time is 20 times faster when compared to traditional, gate-level methodologies. This enables designers to identify and make power decisions early and reliably. By uncovering power reduction opportunities, such as hierarchical clock gating through RTL techniques, powerful interactive debug functionality and power-efficiency metrics, PowerArtist enables power savings as high as 70 percent. PowerArtist also accelerates power profiling that runs several orders of magnitude faster than traditional interval-based power analysis methodologies. This rapid analysis cuts analysis time from weeks to hours, to facilitate the identification of critical peak power and large current transient (di/dt) cycles. It guards the chip against design failures due to undetected scenarios and, more importantly, enables robust power and thermal planning across the chip, package and system.
Accelerate design convergence with big data and actionable analytics
Semiconductor chips for next-generation automotive, mobile and high-performance computing applications — powered by artificial intelligence and machine learning algorithms — require advanced 16nm/7nm systems on chip (SoCs), which are bigger, faster and more complex. For these SoCs, the margins are smaller, schedules are tighter and costs are higher. Faster design convergence with exhaustive coverage is imperative for first-time silicon success. RedHawk-SC — the next-generation SoC power and reliability signoff solution — is based on ANSYS SeaScape big data architecture. This architecture provides elastic scalability to solve a billion-plus instance designs within a few hours. It enables rapid design iterations across multiple scenarios and operating conditions, cutting days of simulations to just a few hours. Using big data analytics, it prioritizes design issues based on multiple competing design attributes. RedHawk-SC in ANSYS 19 provides a 10x acceleration in runtime when compared with traditional EDA solutions. Additionally, the elasticity of RedHawk-SC provides a 10x improvement in hardware resource utilization.
Simulation coverage is key, and the ability to rank and score vectors from various sources — functional, test, vectorless, etc. — is important. Simultaneously simulating multiple scenarios for various PVT corners rapidly accelerates the design development process. With RedHawk-SC, you can explore hundreds of switching scenarios overnight, and rank vectors for dramatic increases in the design coverage. This results in a drastic improvement in signoff coverage versus traditional electronic design automation (EDA) solutions.
Design for reliability
Semiconductor reliability requirements are rapidly evolving. New applications, such as advanced driver assistance systems, self-driving cars and drones, are pushing the limits of system reliability. Increased functionality and power density in next-generation FinFET designs are leading to self-heating of the devices and Joule heating of the wires. These result in wide variation of on-chip temperatures. With narrower wire widths, the electromigration (EM) limits are also decreasing. As a result, increased temperatures lead to more, and more difficult to fix, EM violations on-chip. A comprehensive, thermal-aware EM solution that models self-heat effects and overall junction temperature variation of the die is required for accurate signoff.
Statistical electromigration budgeting (SEB) allows chip designers to meet stringent safety and reliability requirements by prioritizing the most important EM fixes for signoff while avoiding overdesign. Designers can benefit greatly from SEB modeling by fixing only the most critical EM violations that impact product reliability. This significantly reduces reliability signoff efforts from months to a few weeks, accelerating design closure. Totem and RedHawk each offer self-heat and chip-package thermal co-analysis solutions in ANSYS 19. These solutions are supported for advanced FinFET technology nodes (N16 and below) across all major foundries.
Design for electro static discharge integrity and robustness
With the prominent use of IPs and high-speed interfaces in SoCs, electrostatic discharge (ESD) design and verification is becoming extremely challenging. ESD checks are now one of the key signoff metrics. Almost 55 percent of the failures are interconnect-related, and can be avoided by performing systematic ESD checks during the design phase. But ESD protection that works at the IP level may not work at the SoC level due to poor connectivity to other IPs and circuits in the SoC. Therefore, it is important to analyze the ESD protection schemes at the SoC level, across multiple voltage domains, to make sure they provide the intended low-resistance path for discharging a potential ESD event without stressing the functional devices.
PathFinder in ANSYS 19 enables fully distributed machine processing to achieve full-chip, flat ESD signoff for billion-plus instance designs. PathFinder Explorer — the new GUI-based interactive debug platform — promotes rapid design exploration and data mining to gain key insights into design issues to prioritize design fixes. Dynamic ESD analysis now supports FinFET designs. Pathfinder can generate chip ESD compact models for system-level ESD/EMC simulations.