Certification enables users to create power efficient and reliable 5G and artificial intelligence chip sets for high-performance computing, mobile and automotive applications
PITTSBURGH, June 22, 2018 – Customers of Samsung Foundry and Ansys will create the next generation of robust and reliable electronic devices thanks to Samsung Foundry's certification and enablement of Ansys solutions for power integrity and reliability analysis. This certification enables extraction, static and dynamic voltage drop analysis, self-heat and electromigration analysis for both power and signal nets for Samsung Foundry’s latest 7-nanometer Low Power Plus (7LPP) lithography process technology.
Samsung Foundry’s 7LPP is its first semiconductor process technology to use an EUV lithography, a state-of-the-art process technology that greatly reduces complexity and offers significantly better yield and fast turn-around time when compared to its 10-nanometer (10nm) FinFET predecessors.
“With 7LPP process technology, customers are empowered to create transformative products for seamless connectivity with 5G and smart devices with artificial intelligence (AI) in next-generation mobile, HPC and automotive applications,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “By using Ansys solutions certified for 7LPP, our mutual customers can create power efficient 5G mobile chipsets with a smaller footprint for slimmer mobile phone designs and build AI chips for computationally intensive deep learning applications for cloud and edge computing.”
“Ansys and Samsung Foundry have a long history of successfully empowering customers to develop innovative and reliable products by providing comprehensive design methodologies for power integrity, thermal and reliability signoff across the chip, package and system,” said John Lee, general manager at Ansys. “Through the Samsung Advanced Foundry Ecosystem (SAFE) initiative, we continue to provide leading-edge process platforms so our customers can more quickly create robust electronics systems while minimizing design costs and risk.”
Ansys will be featured at the Design Automation Conference (DAC) in booth 1637 from June 24-28 in San Francisco, California.
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