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Synopsys at DesignCon 2026

Booth #919

Visit us at DesignCon 2026 to explore our latest advancements in high-fidelity simulation and electronics design. Discover how our solutions enable engineers to accelerate 3D-IC integration, optimize signal and power integrity, and overcome system-level thermal challenges − empowering breakthrough performance in next-generation high-speed systems.

Date:
February 24-26, 2026

Venue:
Santa Clara Convention Center
5001 Great America Pkwy, Santa Clara, CA 95054

Simulation: From Systems to Silicon

Synopsys enable engineers to master high-speed design, unify signal and power integrity, tackle EMI and thermal challenges, and accelerate verification and validation. Explore how our high-fidelity tools provide actionable insights across 3D-IC packaging, system-level co-simulation, and complex high-speed designs.

Get a firsthand look at Synopsys 224G SerDes IP delivering silicon proven performance across electrical and optical interconnects and a sneak-peak into PCIe 8.0 electrical performance for next generation AI and data center systems.

When systems and chips become smaller, staying cool becomes the hardest job!

Live Presentations

DateTimeSubjectPresentation TitlePresenterLocation
25-Feb1:30 - 2:00 PMScaling Via Optimization with JITX+Ansys+GenAITaming the Combinatorial Explosion: Scaling Via Optimization with JITX+Ansys+GenAICarl Allendorph, Sr. Product Manager and Kenneth Chang, Chief of Staff at JitxBooth #919
25-Feb3:30 - 4:00 PMSolving EM Interaction Issues with Modelithics Measurement-Validated Models for Ansys HFSSSimplifying Complexity: Advanced EM Models for High-Performance DesignsEric O'Dell, VP of Product Development at ModelithicsBooth #919
25-Feb4:30-5:00 PMEliminating low-value tasks with Ansys & Altium increases the amount of time that engineering teams have to focus on what truly matters: innovation.Streamlining Electronics Design & Simulation with Ansys & AltiumJoao Beck, Director of Enterprise Technical Marketing at AltiumBooth #919
26-Feb2:30 - 3:00 PMPCIe 8.0: Engineering for 256 GT/s PCIe 8.0: Engineering for 256 GT/s in the AI EraMadhumita Sanyal, Technical Product Management Director at SynopsysBooth #919
26-Feb4:45 - 6:00 PMPCIe Signaling and Physical TopologiesDesigning & Validating the Future: SERDES & Channel Innovations for PCIe at 128 GT/sPanel DiscussionBallroom A

Speakers

Where to Find Us

Synopsys IP Featuring PCIe 8.0-Class Performance at 256GT/s

The Synopsys booth will feature an exclusive demonstration of next generation 256GT/s electrical performance, including highspeed eye diagram viewing and receiver performance at PCIe 8.0 data-rates.

Hirose Electric Americas – Booth #927

Featuring Synopsys 224G PHY IP interop with Hirose BK35G Flyover Cable and FPC connector 

Samtec – Booth #939

Featuring Synopsys 224G PHY IP on the Samtec SiFly platform, supporting co‑packaged and near‑chip system designs.

Luxshare –  Booth #839

Featuring Synopsys 224G PHY IP transmitting bidirectional data under realistic signal conditions using Luxshare’s Koolio Co- Packed Copper platform.

Teledyne LeCroy – Booth #1149

Featuring Synopsys PCIe 7.0 IP PHY IP with Teledyne LeCroy tools for transmitter equalization, eye‑diagram analysis, SNDR measurement, jitter evaluation, TxFFE tuning, and related characterization tasks.