From Device Physics to PIC Layout: A Unified Lumerical–OptoCompiler Workflow

Overview

Bridging the gap between optical device simulation and circuit-level PIC implementation remains a key challenge in photonic design workflows. This webinar provides a technical deep-dive into the integration of Ansys Lumerical with Synopsys OptoCompiler to enable a consistent, multi-scale design flow from layout to device simulation to layout-aware circuit verification.

We will examine how layout Pcells defined in OptoCompiler can be imported directly into photonic component design tools – Lumerical FDTD, Lumerical MODE, and Lumerical Multiphysics – for robust modeling of 3D photonic devices. We will then see how Lumerical CML Compiler is used to extract device characteristics – such as S-parameters, scattering matrices, and frequency-domain responses – to create parameterized compact models for use in both Lumerical INTERCONNECT (for PIC design and simulation) and OptoCompiler (to enable electro-optic co-simulation). The webinar will detail how the process of mapping device-level simulation data into PDK-ready compact model libraries includes considerations for wavelength dependence, dispersion, loss mechanisms, and fabrication-aware variability.

In addition, we will cover co-simulation workflows that couple INTERCONNECT circuit simulations with OptoCompiler schematic and layout environments, enabling hierarchical validation and layout-driven verification. Emphasis will be placed on maintaining model fidelity across abstraction levels, ensuring consistency between EM-derived device behavior and circuit-level predictions.

What attendees will learn

• Integrated flows from Pcell layout to device-level simulation
• Device simulation and characterization using FDTD/MODE/Multiphysics solvers
• Compact model generation and parameterization for PDK integration
• INTERCONNECT-driven system simulation using physically derived models
• Netlist-to-layout propagation within OptoCompiler
• Layout-aware simulation and verification strategies
• Techniques for reducing model-to-silicon mismatch prior to tapeout

Who should attend

• Engineers working on silicon photonics and advanced PIC design who require tight correlation between device physics, circuit simulation, and physical implementation.

Speaker

• Luis Orbe, Solutions Engineering, Sr Staff Engineer