Elastic Compute Scalable Design Methodologies for Next-Generation FPGAs

Next-generation field programmable gate arrays (FPGAs) for 5G, AI, automotive, cloud and data center applications are getting bigger, faster and more complex. With the market’s continuous demand for higher performance and lower power products, FPGA designers strive hard to achieve stringent power, performance, area and reliability goals to stay ahead of the game. Traditional electronic design automation (EDA) techniques for full-chip critical path timing analysis and power integrity signoff cannot meet the capacity, performance and accuracy requirements for these complex FPGAs. Productivity and project schedules are negatively impacted as a result.

In this webinar, FPGA inventor Xilinx discusses the many applications for its innovative elastic compute scalable design methodologies, including:

  • Large design scaling for timing analysis using ANSYS SeaScape
  • Full-chip EM/IR signoff using ANSYS RedHawk-SC
  • Accelerated chip-scale interconnect delay calculation for timing capture flow using ANSYS Path FX
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