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Ansys at DAC 2023

Join Us at the Design Automation Conference

Dates: July 9th-13th
Booth #1539

 

Schedule a Meeting at DAC Register for the breakfast event
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We're Covering the Latest Technology Trends Researched by Ansys Experts

The semiconductor and electronics industries collide with 3D-IC technology, enabling companies to design differentiating bespoke silicon. The advent of 3D-IC requires more physics domains in a multiphysics challenge with new tools and approaches to building electronic design teams. At DAC 2023, we’ll share the latest 3nm power integrity signoff technologies, dynamic voltage drop coverage, thermal signoff for chips & PCBs, advanced 2.5D/3D packaging, and photonic design.

See the Latest Multiphysics Signoff Technology

Did you know? Ansys delivers the industry’s broadest range of foundry-certified golden signoff tools for semiconductor design, electronic design, and full system design.

Stop by our booth to see the latest advances in Power Integrity, Thermal Analysis, Electromagnetics, and Photonics for semiconductor and board designers. Our technical experts are available to answer your questions. Or you can schedule a meeting in our booth. 

Grab a seat in our booth theater featuring short presentations by our customers, partners, and technologists on a variety of topics at regular intervals during the exhibit hours.

SCHEDULE A MEETING AT DAC
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Keynote information: Hear from Ansys CTO, Prith Banerjee

Tuesday, July 11th, 9:00 am – 9:15 am

Driving Engineering Simulation and Design with AI/ML

Attend the Tuesday morning keynote to hear Ansys CTO Dr. Prith Banerjee present “Driving Engineering Simulation and Design with AI/ML” on Tuesday morning. For more information on this presentation, please visit the DAC Website.

WE'RE SHOWING THE LATEST IN DESIGN TECHNOLOGY

Ansys Redhawk-SC performs IC electrothermal simulations

Address Power Integrity

EM/IR signoff analysis is exponentially more difficult with Dynamic Voltage Drop (DVD), but the new EM/IR analysis and debugging capabilities in the RedHawk-SC ™ family handle it easily.

Learn More
Ansys Signal Power & Integrity

Handle 3D-IC Electrothermal

Heat dissipation is a primary concern for all 2.5D/3D designs, and RedHawk-SC Electrothermal™ includes power integrity, fluid dynamics simulation for thermal cooling, mechanical simulation, and electromagnetic analysis.

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Ansys Electronics Desktop Student Is Added to Free Software Downloads

Analyze and Measure System Reliability & Hardware Security

From power integrity, signal integrity, electromagnetic and thermal simulation, Ansys solutions analyze and measure the vulnerability of silicon circuits to hardware side-channel attacks.

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Modeling Coupling Between Cables and Platforms for Electromagnetic Compatibility with Ansys EMA3D Cable

Manage Electromagnetic Coupling & Interference:

Wi-Fi, 5/6G, and high-speed digital backplanes require accurate electromagnetic modeling, and RaptorX™ delivers the speed and capacity to analyze today's largest silicon designs in a single run.

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Enable RTL Power Analysis & Optimization

Hardware emulators execute real applications, generating enormous quantities of vector data. PowerArtist™ analyzes these vast data streams to extract critical vector subsets that capture peak power and reduce power consumption.

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zemax camera lenses exploded view

Script, Process and Optimize Photonics

The industry's most complete optical design and analysis flow.

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Driving Design Excellence: The Future of Automotive Electronics

Join us!

We're hosting a breakfast panel discussion with industry experts who discuss their experience with innovating for the radically changed automotive landscape with electrified power trains, autonomous navigation, and over-the-air connected vehicles.

Date: Tuesday, July 11th 2023
Time: 7:00AM - 8:30AM
Location: Marriott Marquis, Golden Gate A
780 Mission St, San Francisco, CA

Space is limited, so sign up today to save your spot.

judy curran
Moderator:

Judy Curran, Ansys

Judy is an accomplished senior automotive executive with over 30 years of experience in automotive/mobility engineering, and technology leadership.  She currently is the Sr. Chief Technologist (CTO) Automotive at Ansys: partnering with OEMs and suppliers in their digital transformation.  She is also an independent corporate board director at FORVIA, and MicroVision providing guidance on the automotive industry, and key technologies.

Request a Seat

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Thank you for registering for our breakfast panel, Driving Design Excellence: The Future of Automotive Electronics. You can add the event to your calendar.

Please wear your DAC conference badge to the event.


Panelists

Synopsys (Co-sponsor):

Randy Fish

Dir. Product Line Management, HW Analytics & Test

Intel Foundry Services:

Ajay Sharma

Senior Director Automotive - Strategy & Biz Dev

NVIDIA (Co-sponsor):

Nima Pour Nejatian

Global Head Solutions Architecture and Engineering, Automotive

Vitesco Technologies:

Aravind Ramakrishnan

Head of Partnership & Innovation, West Coast

Rivian:

Vidya Rajagopalan

VP of Engineering, Hardware

Infineon Technologies:

Christian Pacha

Sr. Dir. Platform Architecture - Automotive Microcontroller

Upcoming Workshops

Reserve your spot to attend our Customer Workshops at DAC. With over 22 technical papers from Ansys customers accepted by the DAC Conference, the Workshops are able to deliver 2 hours of technical presentations and discussions from Ansys customers on their experiences and successes using Ansys solutions. There are three Workshop tracks with different themes. They will be held in a private room in the Ansys booth (#1539) and you must register to reserve one of the limited number of seats.

LIVE Workshop
July 10, 2023 10:15 AM
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Designers must use highly accurate software simulation tools to successfully address complex physics coupling in a multi-die system. Learn about the multi-die design challenges and precise ways to tackle novel physics using Ansys multiphysics simulation software.

LIVE Workshop
July 10, 2023 2:00 PM
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Managing a reliable supply voltage is a top priority for every chip designer. We developed breakthrough technologies to address DVD coverage and its impact on timing. Attend this workshop to learn about breakthrough achievements in predicting the dynamic voltage drop scenarios in chips.

LIVE Workshop
July 11, 2023 10:15 AM
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Chip design companies must adopt more aggressive design and production methods, leaving no room for multiple design iterations. In our upcoming workshop, we'll explore the optimized 'Shift Left' approach to design and the importance of multiphysics sign-off in meeting design goals.

Monday, July 10

DATETIMETRACKTITLEAUTHORS
10-Jul10:15am - 11:15amDAC Pavilion PanelBest of Both Worlds – Bridging the Gap between EDA, System and ManufacturingJohn Lee - VP and GM Electronics, Semiconductors, and Optics Group, Ansys
10-Jul11:15am - 11:30amBack-End DesignHigh Bandwidth Memory (HBM3-7.2Gbps) 2.5D-IC Integration with Signal Interconnects and Power Distributed Networks Design-OptimizationSam Yang - Global UniChip Corp.
Joseph Wang - Global UniChip Corp.
Ethan Lin - Global UniChip Corp.
Justin Hsieh - Global UniChip Corp.
10-Jul11:30am - 11:45amBack-End DesignThermal Aware Vectorless EM/IR signoff for High Speed Custom Digital IPsAyan Roy Chowdhury - Intel
10-Jul1:30pm - 5:00pmTutorialSide-Channel Analysis: from Concepts to Simulation and Silicon ValidationGang Qu - University of Maryland, Imperial College London
Makoto Nagata - University of Kobe
Lang Lin - Ansys
10-Jul4:45pm - 5:00pmFront-End DesignUnique metric driven vector qualification and Ranking for peak power coverageSeunghyeon Park - Samsung Electronics
Jinsuk Youn - Samsung Electronics
Wojoo Kim - Samsung Electronics
Kunhyuk Kang - Samsung Electronics
10-Jul5:00pm - 6:00pmEngineering Poster TrackAggressor Aware Design for Better IRdrop ResultsVlad Berlin - Retym
Eddie Reizin - Retym
Boris Shapiro - Ansys
10-Jul5:00pm - 6:00pmEngineering Poster TrackPower Integrity analysis of 3D stacking Structure in CMOS Image Sensor ChipEric Chen - Omnivision
Xiaodong Wang - Ansys
Li Yahui - Ansys
10-Jul5:00pm - 6:00pmEngineering Poster TrackA Comprehensive Thermal Solution in Advanced Large Scale 3DIC DesignKeqing Ouyang - Sanechips Technology Co.,Ltd
Ping Ding - Sanechips Technology Co.,Ltd
Junjie Chen - Sanechips Technology Co.,Ltd
Guohua Zhou - Sanechips Technology Co.,Ltd
Haodong Lei - Sanechips Technology Co.,Ltd
Li Zou - Ansys
Chang Zhao - Ansys

Tuesday, July 11

DATETIMETRACKTITLEAUTHORS
11-Jul9:00am - 9:15amVisionary TalkDriving Engineering Simulation and Design with AI/MLPrith Banerjee - CTO, Ansys
11-Jul5:00pm - 6:00pmEngineering Poster TrackA Novel Fitting Method of Package Material Parameters Base On MOPXinxin Dong - Sanechips Technology Co.,Ltd
Yongsheng Guo - Ansys
Feng Wu - Sanechips Technology Co.,Ltd
Yuan Kai - Sanechips Technology Co.,Ltd
Jiangtao Zhang - Sanechips Technology Co.,Ltd
Keqing Ouyang - Sanechips Technology Co.,Ltd
11-Jul5:00pm - 6:00pmEngineering Poster TrackA Multiphysics Simulation Flow for High Performance MMIC Products for Power 5G and RF ApplicationsVittorio Cuoco - Ampelon
11-Jul5:00pm - 6:00pmEngineering Poster TrackStatistical IR Analysis with Ansys SigmaDvDPranav Ranganathan - Microsoft
Chip Stratakos - Microsoft
Medha Kulkarni - Microsoft
11-Jul5:00pm - 6:00pmEngineering Poster TrackSPICE Validation of Dynamic Voltage Drops from SigmaDVDAndy Hoover - Samsung Electronics
Kevin Klein - Samsung Electronics
Ed Deeters - Ansys
Jeff Linn - Ansys
11-Jul5:00pm - 6:00pmEngineering Poster TrackA design analytics-based methodology for enhancing Dynamic IR signoff with minimum design changesAmit Singh - STMicroelectronics
Govind Pal - STMicroelectronics
Sanjeev Jain - STMicroelectronics
Anil Yadav - STMicroelectronics
Atul Bhargava - STMicroelectronics
Amit Jangra - Ansys
Koshy John - Ansys
11-Jul5:00pm - 6:00pmEngineering Poster TrackPre-Silicon Power Side-channel Security Verification for Crypto IPsAmitabh Das - AMD
Emrah Karagoz - AMD
Geethu Babu - Ansys
Sreeja Chowdhury - Ansys
11-Jul5:00pm - 6:00pmEngineering Poster TrackA novel methodology for EM/IR analysis of Complex LDO/Power gated designsPavan Bilekallu - Qualcomm
Debprasad Nandi - Qualcomm
Ranjini Gowda - Qualcomm
11-Jul5:00pm - 6:00pmEngineering Poster TrackEarly IR Drop Prediction using Machine Learning for Power GridAnil Dsouza - Intel
Anantha Krishnan A.K - Intel
Ayan Roy Chowdhury - Intel

Wednesday, July 12

DATETIMETRACKTITLEAUTHORS
12-Jul5:10pm - 5:20pmEngineering Poster TrackAn Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery NetworkYuanyuan Ling - Iluvatar
Ling Sun - Iluvatar
Tieqing Chen - Iluvatar
Zhenhua Gan - Iluvatar
Shixuan Que - Iluvatar
Shuqiang Zhang - Iluvatar
Xiaoxia Zhou - Iluvatar
12-Jul5:18pm - 5:28pmEngineering Poster TrackAutomated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCsManish Kumar - STMicroelectronics
Govind Pal - STMicroelectronics
Samant Paul - STMicroelectronics
Anil Yadav - STMicroelectronics
Atul Bhargava - STMicroelectronics
Amit Jangra - Ansys
Koshy John - Ansys
12-Jul5:19pm - 5:29pmEngineering Poster TrackBridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics DesignsSrim Karthik Kanneganti - Intel
12-Jul5:33pm - 5:35pmEngineering Poster TrackHigh-Performance Design with Rapid RTL Profiling of Critical Power ScenariosAlexander Pivovarov - AMD
Vidhu Joshi - AMD
Mehdi Sadi - AMD
12-Jul5:38pm - 5:48pmEngineering Poster TrackIntegration of Intel Thermal Model with Design-for-Reliability FlowLei Jiang - Intel
Daniel Pantuso - Intel
Prabhakar Marepalli - Intel
Colin Landon - Intel
Mohammed Shahid - Intel
Sanjay Murthy - Intel
Mike Wang - Intel
12-Jul5:44pm - 5:54pmEngineering Poster TrackNovel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)Matthew Jastrzebski - Intel
Roger Hayward - Intel
Noel Pereira - Intel
12-Jul5:46pm - 5:57pmEngineering Poster TrackNovel Chip-Package-System thermal analysis with RTL PowerChenyang Zhang - Sanechips Technology Co.,Ltd
Zhongming Hou - Ansys
Chen Lin - Sanechips Technology Co.,Ltd
Shuqiang Zhang - Ansys
Bin Guo - Sanechips Technology Co.,Ltd
12-Jul5:47pm - 5:57pmEngineering Poster TrackNovel Hierarchical IREM Sign-off Flow using ROMDongyoun Yi - Samsung Electronics
Seonghun Jeong - Samsung Electronics
Byunghyun Lee - Samsung Electronics
12-Jul5:53pm - 5:59pmEngineering Poster TrackSigmaDVD (sDVD): High Coverage Solution for Power Integrity SignoffAnusha Vemuri - NVIDIA
Emmanuel Chao - NVIDIA
Santosh Santosh - NVIDIA
Chidambaram Rakkappan - Ansys
Ed Deeters - Ansys

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