Simulation World Silicon Valley

Name: Simulation World Silicon Valley
Start: 2025-09-01T04:00:00Z
End: 2025-09-01T04:00:00Z

Wednesday, September 10, 2025
8:00 AM - 3:30 PM PDT

Santa Clara Marriott
2700 Mission College Blvd,
Santa Clara, CA 95054

What's On
Agenda
Speakers
Partners

Event Highlights

As a part of the Simulation World 2025 event series, this event offers expert-led sessions, real-world success stories, and valuable insights into the Ansys simulation strategy. Hear from leading industry speakers showcasing their innovative use of simulation and discover tools to optimize processes and turn bold ideas into reality.

What You'll Experience

Technical Tracks

Explore technologies and workflows designed to optimize processes and turn breakthrough ideas into reality with speed and efficiency.

Inspiration and Networking

Engage with Ansys experts, network with peers, share experiences, and build confidence to design, build, and innovate in new ways.

Agenda

General Session

8:00 AM - 9:00 AM	Registration & Breakfast
9:00 AM - 9:15 AM	Welcome
9:15 AM - 9:40 AM	Industry Keynote: Realizing Accelerated Simulation for Semiconductor Manufacturing Presented by: Dr. John Linford, Head of Product, Industrial Engineering
9:40 AM - 10:00 AM	Keynote Presentation: Strategic View of Simulation Presented by: Dr. Prith Banerjee, Senior Vice President for Simulation and Analysis Incubation Group, Synopsys
10:00 AM - 10:45 AM	Panel Discussion: Designing Chips-to-Systems for an AI-Driven World Moderated by Dr. Prith Banerjee, Senior Vice President for Simulation and Analysis Incubation Group, Synopsys Ravi Subramanian, Chief Product Management Officer, Synopsys Nidhi Chappell, Vice President & General Manager, Azure AI and HPC, Microsoft Alex Starr, Vice President and Fellow, AMD John Linford, Head of Product CAE/EDA, NVIDIA Abstract: This conversation will explore how chips-to-systems design is evolving to meet the demands of an AI-driven world. By integrating silicon design with system-level simulation, organizations are unlocking faster, more reliable innovation across increasingly intelligent and connected products.
10:45 AM - 11:00 AM	Networking Break

Track 1 - Signal & Power Integrity

11:00 AM - 11:30 AM	Shift Left: AI, JITX, Ansys HFSS, and the Future of PCB Design Presented by: Carl Allendorph, Senior Product Manager, JITX Inc.
11:30 AM - 12:00 PM	AEDT 2025R1 and 2025R2 Ansys AEDT Product Updates Presented by: Sara Louie, Principal Product Manager, Synopsys
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	Electromagnetic Modeling and Simulation Challenges for Silicon Interposers in 2.5D/3D IC Chip Design Presented by: Skanda Kotethota, Lead Application Engineer, Synopsys
1:30 PM - 2:00 PM	Design Challenges and Considerations for Reliable Rigid-Flex PCB up to 100GHz Presented by: Juliano Mologni, Principal Product Manager, Synopsys
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Emag-Aware ML-Based Layout and Design Optimization of RF and High-speed ICs Presented by: Bryan Prebble, Principal Application Engineer, Synopsys
2:45 PM - 3:15 PM	Automated Workflows in AEDT Presented by: Isaac Waldron, Manager Application Engineering, Synopsys
3:15 PM - 3:30 PM	Track Wrap Up: Signal & Power Integrity Presented by: Aaron Edwards, Senior Director Application Engineering, Synopsys

Track 2 - Low Frequency Electromagnetics

11:00 AM - 11:30 AM	From Silicon to Systems: A Low-Frequency Electromagnetic Perspective Presented by: Mark Solveson, Principal Product Manager, Synopsys
11:30 AM - 12:00 PM	Optimize Wireless Charging for Consumer Electronics to Car Infotainment Systems Presented by: Jingchen Liang, Lead Application Engineer, Synopsys
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	Low Frequency Electromagnetic Solutions for PCB Design and Component EMI/EMC Presented by: Tianze Kan, Lead Application Engineer, Synopsys
1:30 PM - 2:00 PM	Motor Optimization with Ansys Electronics Desktop & HPC Presented by: Yuanying Wang, Technical Specialist, Lucid Motors
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Electric Motor Design and Multidisciplinary System Integration for Robotics Presented by: Shi-Uk Chung, Senior Application Engineer, Synopsys
2:45 PM - 3:15 PM	Electric Power System for Data Centers Presented by: Kamyar Keikhorsravy, Senior Application Engineer, Synopsys
3:15 PM - 3:30 PM	Track Wrap Up: Low Frequency Electromagnetics Presented by: Pavani Gottipati, Senior Manager Application Engineering, Synopsys

Track 3 - Electrothermal & Multiphysics Solutions

11:00 AM - 11:30 AM	End-to-End Multiphysics Simulation Framework for Automotive ECU Design Validation Presented by: Omkar Gokhale, Senior Thermal Engineer, Lucid Motors
11:30 AM - 12:00 PM	Modeling Two-Phase Liquid Cooling for Advanced Electronics Thermal Management Presented by: Sreenivas Viyyuri, Lead Application Engineer, Synopsys
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	Multi-Physics Modeling and Validation of a SiC Power Module for EV Traction Inverter Using Ansys Simulation Tools Presented by: Leon Zhang, Senior Manager for Power Module Design, Onsemi
1:30 PM - 2:00 PM	Design Cooler, Fail Less: Electronics Cooling with Ansys Icepak and Ansys Discovery Presented by: Joey Du, Senior Applications Engineer, Synopsys
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Increasing Productivity with Physics-Aware Reduced Order Component Models as Digital Twins Presented by: Bogdan Ionescu, Senior Principal Key Expert, Innomotics
2:45 PM - 3:15 PM	Fast and Efficient Thermal Control using Dynamic Thermal Management (DTM) in Ansys Icepak and Twinbuilder Presented by: Nikhil Tamhankar, Senior Applications Engineer, Synopsys
3:15 PM - 3:30 PM	Track Wrap Up: Electrothermal & Multiphysics Solutions Presented by: Jared Harvest, Manager Application Engineering, Synopsys

Track 4 -Semiconductor

11:00 AM - 11:30 AM	A Novel Approach for Workload-Based GPU Datapath Power Optimization Presented by: Deepayan Dasgupta, Tanuj Sengupta, Samsung Austin Research Center
11:30 AM - 12:00 PM	Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach Presented by: Sai Atluri, Application Engineer, Synopsys
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	For the Sigma Technologies: High Coverage Power Integrity Signoff Solution for Reliable IR-drop Fixing and Power Grid Evaluation Across Process Nodes/Design Presented by: Anusha Vemuri, Nvidia; Amogh Sakdeo, Nvidia; Vishal Malik, Nvidia; Emmanuel Chao, Nvidia; Santosh Santosh , Nvidia
1:30 PM - 2:00 PM	Cost and compute-efficient IR Drop hierarchical signoff for Subsystems Presented by: Krishna Yellamilli, Senior Manager Application Engineering, Synopsys
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Reducing High di/dt Simultaneous Switching Noise in Advanced Multiprocessor SoCs Presented by: Ravi Thiruveedhula, Principal Application Engineer, Synopsys
2:45 PM - 3:15 PM	Accurate Thermal Simulation of Multi-Die Packages with Co-Packaged Optics. Presented by: Lang Lin, Principal Product Manager, Synopsys
3:15 PM - 3:30 PM	Track Wrap Up: Semiconductors

Track 5 - Optics, Photonics and Enabling Technologies

11:00 AM - 11:30 AM	Photonic INTERCONNECT Optimization Presented by: Marco Fiorentino, Senior Distinguished Technologist, HPE
11:30 AM - 12:00 PM	Toward Intelligent Infrastructure Linking Photonic Integrated Circuit Physical Design to System-Level Simulation Presented by: Ahmadreza Farsaei, Principal Software, Intel
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	Multiphysics Simulation on Calibration of XR devices Presented by: Philip Brune, Calibration Engineer, Google
1:30 PM - 2:00 PM	Connecting Lighting with Accurate Sensor Simulation for Automotive Regulation Compliance (FMVSS 127 and ADB) Presented by: Matt Paquet, Principal Application Engineer, Synopsys
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Overview of Ansys CPO Solutions with focus on Optical I/O Presented by: Fatema Chowdhury, Manager Application Engineering, Synopsys
2:45 PM - 3:15 PM	Multphysics Simulation for Camera Sensors Presented by: Vikas Singh, Technical Specialist, Lucid
3:15 PM - 3:30 PM	Track Wrap Up: Optics, Photonics, & Enabling Technologies

Track 6 - Design for Structural Reliability and Semiconductor Manufacturing

11:00 AM - 11:30 AM	Design for Reliability - Simulation Automation & AI/ML Strategies for Electronics Reliability Presented by: Kelly Morgan, Senior Principal Application Engineer, Synopsys
11:30 AM - 12:00 PM	Efficient Simulation of Multi-Bend Process and Springback of Flexible Printed Circuit Boards Presented by: Shams Arifeen, Technical Lead, Google
12:00 PM - 1:00 PM	Lunch Break
1:00 PM - 1:30 PM	Optimized Simulation Methodology of Warpage and Localized Stress Hotspot Prediction for Assembly Risk Management Presented by: Zhi Yang, Senior Director, Groq
1:30 PM - 2:00 PM	Addressing Thermomechanical Challenges in Advanced Packaging with FE Simulation Presented by: Arkaprabha Sengupta, Principal Engineer, Samsung
2:00 PM - 2:15 PM	Networking Break
2:15 PM - 2:45 PM	Simulation of Wafer to Package Manufacturing Processes Presented by: Devashish Sarkar, Manager Application Engineering, Synopsys Harish Kanchi, Manager Application Engineering, Synopsys
2:45 PM - 3:15 PM	Ansys Charge Plus Simulation for Integrated Circuits( ICs) Presented by: Kevin-Druis Merenda, Principal Scientist and Product Manager, Synopsys
3:15 PM - 3:30 PM	Track Wrap Up: Design for Structural Reliability and Semiconductor Manufacturing

Keynote Speakers and Panelists

Prith Banerjee

Senior Vice President for Simulation & Analysis Incubation Group at Synopsys

Dr. Prith Banerjee is the Senior Vice President for Simulation & Analysis Incubation Group at Synopsys, where he leads the company’s technology strategy and drives innovation for its next phase of growth. With an extensive background in academia and industry, he has held leadership roles at Schneider Electric, ABB, Accenture, and Korn Ferry, and has been recognized for his contributions to electronic design automation and parallel computing.

Nidhi Chappell

Vice President & General Manager, Azure AI and HPC, Microsoft

Nidhi Chappell is a visionary tech leader with over 15 years of experience spanning engineering, product management, and strategic planning. She has a proven track record of scaling businesses from millions to billions in revenue and driving innovation through transformative initiatives like the OpenAI engagement. Known for her ability to turn complex challenges into scalable solutions, Nidhi is also a dynamic speaker and dedicated mentor. She is passionate about empowering teams and fostering diversity in the technology sector.

JohnLindford_NVIDIA - John Lindford NVIDIA

John Linford

Head of Product EDA/CAE, NVIDIA

Dr. John Linford leads NVIDIA's industrial engineering product team and is based in Austin, TX. He holds a Ph.D. from Virginia Tech, where he earned the Outstanding Dissertation Award for his work on accelerated numerical methods. His expertise includes high-performance simulation, software optimization, and pre-silicon design. Throughout his career, he has contributed to radar signal processing, HPC consulting, and technical leadership at Arm Ltd.