Empower Innovation at IDEAS 2023 Digital Forum

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Dr. Prith Banerjee is the Chief Technology Officer of Ansys. He is responsible for leading the evolution of Ansys’ Technology strategy and will champion the company’s next phase of innovation and growth. Previously, he was Senior Client Partner at Korn Ferry where he was responsible for IOT and Digital Transformation in the Global Industrial Practice. Prior to that, he was Executive Vice President, Chief Technology Officer of Schneider Electric. Previously, he was Managing Director of Global Technology Research and Development at Accenture. Formerly, he was Chief Technology Officer and Executive Vice President of ABB, a power and automation company in Zurich, Switzerland. Earlier, he was Senior Vice President of Research at HP and Director of HP Labs. Formerly, he was Dean of the College of Engineering at the University of Illinois at Chicago. Formerly, he was the Walter P. Murphy Professor and Chairman of Electrical and Computer Engineering at Northwestern University. Prior to that, he was Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. In 2000, he founded AccelChip, a developer of products for electronic design automation, which was acquired by Xilinx Inc. in 2006. During 2005-2011, he was Founder, Chairman and Chief Scientist of BINACHIP Inc., a developer of products in electronic design automation. His research interests are in electronic design automation, and parallel computing, and he is the author of about 350 research papers in journals and conferences. He was listed in the FastCompany list of 100 top business leaders in 2009. He is a Fellow of the AAAS, ACM and IEEE, and a recipient of the 1996 ASEE Terman Award and the 1987 NSF Presidential Young Investigator Award. He received a B.Tech. (President's Gold Medalist) in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana

Lalitha Immaneni is a Vice President of Engineering in the Assembly Test Technology Development organization for Intel Corporation. Lalitha manages the “Architecture, Design & Technology Solutions” team, which spans multiple geographies such as the United States, Malaysia, and India. She is responsible for substrate/silicon assembly and board design rule development. She designs building blocks for emerging package technologies and electrical and physical design methodologies for packaging, executes product package design, provides product electrical analysis support, and drives product architectures for Intel. Lalitha owns centralized package and board flows/tools for Intel’s packaging and board design needs and enables EDA ecosystem readiness. She also leads architecture and design enabling services for Intel Foundry. Recently, she led the delivery of Intel Foundry Services’ Package Assembly Design Kit. She is currently focused on EDA ecosystem enablement, interoperable formats, and standards for chiplets. Presently, Lalitha is the Assembly Test Technology Development Staff-level Diversity & Inclusion team sponsor and a formal mentor, coach, and sponsor to many technical females and diverse employees. She holds both bachelor’s and master’s degrees in computer science from Arizona State University, with an emphasis on computer graphics and software engineering.

Chip leads the Physical Design team for the AI custom silicon products at Microsoft. He started his career at Intel and also worked at Broadcom and Google. He holds a BSEE from Stanford.

3D-IC RV CAD Engineer at Intel, focused on delivering 3D EMIR solutions to client and servers teams

With over 10 years of experience in the semi-conductor industry, Alexander has had significant exposure to design verification and power convergence, both at IP level and at SoC. He has worked on analyzing and driving power optimization across numerous projects and has developed novel methodologies for getting more accurate results.

Dr. Luca Ramini is a research scientist in the Large Scale Integrated Photonics Lab at Hewlett Packard Enterprise. Luca’s research interests include the design of photonics circuits and optical networks. Luca was Postdoc at the University of Ferrara, contract Professor at the University of Verona, and photonics designer at STMicroelectronics.

Mohit has 7+ years of experience in the field of Design Automation, Standard cell and IO development. At Arm, as a Staff Software Engineer, I am responsible for the methodology implementation, looking after the EDA issues which are raised at Arm.  

I am a Lead Engineer, Layout at Qualcomm. I work with the team to enable the Totem EM/IR analysis tool for reliability tests of the modules.

Love Gupta holds a Bachelor’s degree in Electronics Instrumentation and Control engineering from Thapar University, Patiala. He has around 11 years experience in VLSI industry. During this time he is mainly working with PDN tools for EMIR closure of complex Automotive SoCs. He is also involved in developing PDN design flow methodologies for new technology nodes.

Dr. Garth Sundberg is a Senior Principal Engineer at Ansys where he works with on-die electromagnetic extraction including signal and power integrity, RF-IC, interposers, quantum computing, and die/package co-simulations. He also works on system level signal and power integrity, electrical and thermal modeling of PCBs, connectors, and EMI/EMC.

Anusha Vemuri works at NVIDIA as a Physical Design Methodology Engineer in the Hardware-VLSI team. She studied at UCLA for her Bachelors and Masters in Electrical Engineering and graduated in December, 2020.

Andy Chan is an award-winning, innovative, and customer-focused leader for Microsoft Azure's semiconductor community, with over 20 years of experience in Semiconductor and HPC-related roles. Andy is also a member of Microsoft's Platinum Club, which recognizes and rewards individuals who consistently perform at the highest level and directly contribute to the company's success. He is based in Portland, Oregon.

Ding Ping, joined Sanechips in 2019 and worked in Backend Design Dept.. Mainly engaged in chip power integrity signoff and power consumption analysis and other related work. Have extensive experience in power signoff for advanced process nodes.

Joaquin Matres received his Engineering (2009), M.Sc. (2010) and PhD (2014) degree in Telecommunications from the Universidad Politecnica de Valencia, Spain. For his PhD he built CMOS-compatible all-optical switches and logic gates at IMEC and CEA-LETI foundries. During his 6 month internship in Intel Corporation and 2.5 years in Hewlett Packard Labs, he worked on hybrid tunable lasers, wavelength selective switches and microring based optical transceivers. Then as the first engineer that joined PsiQuantum he worked on design, layout and validation of large scale Quantum computing circuits, where he was involved in most tapeouts during 3 years. Since 2020 Joaquin has been working at X Moonshot Factory (Formerly known as Google X) developing Free Space Optical Transceivers to bring affordable internet to developing countries. Joaquin is also an active developer of many open source projects such as gdsfactory

Joaquin Matres received his Engineering (2009), M.Sc. (2010) and PhD (2014) degree in Telecommunications from the Universidad Politecnica de Valencia, Spain. For his PhD he built CMOS-compatible all-optical switches and logic gates at IMEC and CEA-LETI foundries. During his 6 month internship in Intel Corporation and 2.5 years in Hewlett Packard Labs, he worked on hybrid tunable lasers, wavelength selective switches and microring based optical transceivers. Then as the first engineer that joined PsiQuantum he worked on design, layout and validation of large scale Quantum computing circuits, where he was involved in most tapeouts during 3 years. Since 2020 Joaquin has been working at X Moonshot Factory (Formerly known as Google X) developing Free Space Optical Transceivers to bring affordable internet to developing countries. Joaquin is also an active developer of many open source projects such as gdsfactory

Dr. Bowen Wang became a Senior Staff Process Development SiPho Integration Engineer at Tower Semiconductor at 2022, where he dedicated his expertise to advancing the company's photonic platform development. Piror to this, he served as a Senior Engineer at Synopsys, focusing on enabling photonic Electronic Design Automation (EDA). Dr. Wang boasts over 15 years of experience in the field of photonic integrated circuits, and he earned his PhD in applied physics from Eindhoven University of Technology in the Netherlands.

Keith Lanier received his BS Electrical Engineering degree from North Carolina State University in 1986 and MS Electrical Engineering degree from National Technological University in 1993. From 1986-1994, he worked at Analog Devices in Greensboro, NC designing high accuracy, high speed ADCs and discrete amplifiers. From 1994-2000, he worked as a Physical Verification product applications engineer and manager at ISS and Avant! in RTP, NC. At Synopsys since 2002, he was one of the earliest custom design product champions with many different roles including Product direction, R&D, Quality, and Release Management and is currently a member of the Product Management team within the Synopsys EDA Group focused on Custom, Analog and Mixed Signal, and RF Design products.

Dr. Garth Sundberg is a Senior Principal Engineer at Ansys where he works with on-die electromagnetic extraction including signal and power integrity, RF-IC, interposers, quantum computing, and die/package co-simulations. He also works on system level signal and power integrity, electrical and thermal modeling of PCBs, connectors, and EMI/EMC.

Andy Hoover is the technologist for the Samsung Austin R&D Center (SARC). His 30 years experience spans device engineering, SPICE model generation, RTL design, physical design, circuit design, and design methodology. Among other things, he champions SARC’s use of SigmaDVD, collaborating with Ansys for the past 3 years.

Ayan Roy Chowdhury has done his graduation in Electrical Engg from Jadavpur University, India and completed masters in theoretical Computer Sc with VLSI CAD major from Indian Statistical Institute (ISI), Kolkata, India. He has 16 years of industry experience in design automation areas, focussing on backend design and signoff domains including Simulation, EM/IR, ESD, Physical verification, Extraction & Timing signoff in Intel. His special interest has been Power delivery & EM/IR where he has enabled tools & flows for different generations of internal & external technology nodes and architected signoff methodologies for IPs & SOCs in Intel. He has 15+ publications in Intel internal and different external conferences.

Yuanyuan Ling has 5 years of work experience in system level power integrity(PI) analysis. She is working at iluvatar as a power engineer, mainly focus on new PI methodology development and droop optimization for high performance GPGPU. Before that, she was at Intel for 3 years and responsible for providing package and platform power integrity solution for INTEL server CPU.

Love Gupta holds a Bachelor’s degree in Electronics Instrumentation and Control engineering from Thapar University, Patiala. He has around 11 years experience in VLSI industry. During this time he is mainly working with PDN tools for EMIR closure of complex Automotive SoCs. He is also involved in developing PDN design flow methodologies for new technology nodes.

Tim McDonald is President at EMA. EMA is a leading developer of technologies for engineering simulation. EMA’s engineering specialty is in applied electromagnetics. In this domain, EMA provides software and services to promote the design, certification, and performance of customers’ products. EMA is the Ansys Technology Partner behind the Ansys Electronics Plus solutions of EMC Plus and Charge Plus. Dr. McDonald holds a PhD in Applied Physics and Applied Math from Columbia University in the City of New York.

Dongyoun Yi is a staff engineer at Samsung Electronics. He is currently in charge of EMIR sign-off methodology. He received the B.S. degree in computer science enginerring and the M.S. degree in electronic engineering from Seoul National University in 2010 and 2017, repectively.

Dr. Ki Wook Jung graduated in 2020 with his Ph.D. in Mechanical Engineering at Stanford. He has a strong background in MEMS fabrication techniques, and embedded cooling solutions for high-power density electronics. He is currently working on developing thermal-aware design methodology for 2.5D/3D IC multi-die systems at Samsung Foundry Business.

Gilles has been working with Cadence since 1989. He has lead the photonics efforts and collaboration with partners for the past 8 years.

Kiran Adhikari is a Hardware Engineer in the Azure Hardware Systems & Infrastructure group at Microsoft where he collaborates with cross-functional teams to deliver industry-leading hardware solutions improving PPA and providing faster path to design convergence. He has done extensive work in identifying bottlenecks for physical design execution and played a pivotal role in shaping physical design flows and methodologies. Prior to this, Kiran worked at Intel, focusing on physical design & SOC integration. This involved navigating complex design challenges and delivering solutions for seamless integration. Kiran received his Master of Science in Computer Engineering from Virginia Tech in 2013.

Kenneth Larsen is a product marketing director in the Digital Design Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision, marketing strategy, inspiring product development teams, translating technology concepts into customer solutions, developing high-performance global organizations, conceiving and driving new and emerging products to scale from the ground up, guiding marketing, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School, and Artificial Intelligence at MIT Sloan School of Management.

Yuanyuan Ling has 5 years of work experience in system level power integrity(PI) analysis. She is working at iluvatar as a power engineer, mainly focus on new PI methodology development and droop optimization for high performance GPGPU. Before that, she was at Intel for 3 years and responsible for providing package and platform power integrity solution for INTEL server CPU.

A physical design engineer and leading the power integrity activity at Retym. I have worked as a Senior application engineer at Ansys, and before that I was an SI\PI engineer at Intel MIG group.

James Victory is currently a Fellow at onsemi, working in modeling and simulation for power discrete and module technologies. In June 2008, he co-founded Sentinel IC Technologies. Prior to that, he was the Executive Director of IC Design Enablement at Jazz Semiconductor. He started his career with Motorola in 1992 where he specialized in semiconductor device modeling for RF-analog and power technologies. He received his BSEE, MSEE, and Ph. D in electrical engineering from Arizona State University in 1990, 1992, and 1994 respectively. He has over 50 publications, including invited papers & workshop tutorials on semiconductor device modeling. He holds 6 US patents.