Synopsys at Embedded World 2026

Most Automotive MPU Strategies Have Hidden Safety Flaws, Is Yours One of Them? Hear from Kevin to explore current MPU validation challenges and testing processes on hardware but more importantly shows through case study, that virtual prototypes can give a significant boost in testing efficiency and test coverage.

Usage of Formal Methods in Embedded Software Development to Automate Test Case Generation Based on Model Coverage Gaps. This presentation introduces a Model Coverage Assistant (MCA), which improves software verification efficiency by automating coverage analysis tasks at model level. MCA applies formal methods to identify untestable points or generate test cases, reducing manual effort and saving up to 70% in V&V time.

Informed Systems Engineering Decision-making Through SysML v2 Modelling with Architecture Simulation. This session present a methodology that integrates system architecture modelling with architecture-level simulation to close this gap. The workflow builds on SysML v2 models, enriched with domain-specific libraries, to capture requirements, system concepts, and hardware/software abstractions.

Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads. The RISC-V ISA provides opcode space to encode custom instructions, typically operating on RISC-V’s register file. This can offer meaningful speedups. For higher performance, parallel processing is needed in the form of instruction-level parallelism (ILP) and data-level parallelism (DLP). We'll discuss the concepts for custom extensions to the RISC-V ISA, for application-specific workloads and illustrate the effectiveness of this approach with case studies.