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Take a Leap of Certainty at DAC 2022

Join Us at the Design Automation Conference

Date: July 10th-14th
Venue: Moscone Center, San Francisco, Booth #1539

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We’re covering the latest technology trends researched by Ansys experts

The semiconductor and electronics industries collide as 3D-IC technology, enabling companies to design differentiating bespoke silicon. The advent of 3D-IC requires more physics domains in a multiphysics challenge requiring new tools and approaches to building electronic design teams. At DAC 2022, we’ll share the latest technologies for 5nm power integrity signoff, dynamic voltage drop coverage, electrothermal signoff for chips & PCBs, advanced 2.5D/3D packaging, and photonic design.

See the Latest Multiphysics Signoff Technology

Did you know? Ansys delivers the industry’s broadest range of foundry-certified golden signoff tools for semiconductor design, electronic design, and full system design.

Stop by our booth to see the latest advances in Power Integrity, Thermal Analysis, Electromagnetics, and Photonics for semiconductor and board designers. Our technical experts are available to answer your questions. Or you can schedule a meeting in our booth. 

Grab a seat in our booth theater featuring short presentations by our customers, partners, and technologists on a variety of topics at regular intervals during the exhibit hours. While there, you just might pick up a unique NFT. 

gold cpu chip

Learn From the Experts at DAC

We're participating in the DAC Pavilion Roundtable Discussion on "Bespoke Silicon" where industry experts look at the technical and business implications of companies increasingly turning to tailored silicon solutions to differentiate their key products.

Listen to Ansys experts and customers present actual semiconductor projects during DAC’s Engineering Tracks and Poster Session


Ansys Redhawk-SC performs IC electrothermal simulations

Address Power Integrity

EM/IR signoff analysis is exponentially more difficult with Dynamic Voltage Drop (DVD), but the new EM/IR analysis and debugging capabilities in the RedHawk-SC ™ family handle it easily.

Ansys Signal Power & Integrity

Handle 3D-IC Electrothermal

Heat dissipation is a primary concern for all 2.5D/3D designs, and RedHawk-SC Electrothermal™ includes power integrity, fluid dynamics simulation for thermal cooling, mechanical simulation, and electromagnetic analysis.

Ansys Electronics Desktop Student Is Added to Free Software Downloads

Analyze and Measure System Reliability & Hardware Security

From power integrity, signal integrity, electromagnetic and thermal simulation, Ansys solutions analyze and measure the vulnerability of silicon circuits to hardware side-channel attacks.

Modeling Coupling Between Cables and Platforms for Electromagnetic Compatibility with Ansys EMA3D Cable

Manage Electromagnetic Coupling & Interference:

Wi-Fi, 5/6G, and high-speed digital backplanes require accurate electromagnetic modeling, and RaptorX™ delivers the speed and capacity to analyze today's largest silicon designs in a single run.

PCB Images

Enable RTL Power Analysis & Optimization

Hardware emulators execute real applications, generating enormous quantities of vector data. PowerArtist™ analyzes these vast data streams to extract critical vector subsets that capture peak power and reduce power consumption.

zemax camera lenses exploded view

Script, Process and Optimize Photonics

The industry's most complete optical design and analysis flow.

Schedule of Events

Date Time Track Title Authors
July 12

3:30pm - 5:30pm Research Panel What are the big opportunities in the next renaissance of EDA? Organizer - X. Sharon Hu - University of Notre Dame
Moderator - Jason Cong - University of California, Los Angeles
Sankar Basu - NSF
Timothy Green - Semiconductor Research Corporation
Prith Banerjee - Ansys
Jan Rabaey - University of California, Berkeley
Tim Cheng - Hong Kong University of Science and Technology
Jayanthi Pallinti - APD
July 12 3:30pm – 5:00pm Engineering Track
New Directions in Silicon Solutions Yervant Zorian - Synopsys
Sudip Nag - Xilinx
Norman Chang - Ansys
July 13 2:00pm - 2:45pm DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance Moderator - John Lee – Ansys
Mathew Kaipanatu – Google
Prashant Varshney - Microsoft
Kam Kittrell – Cadence Design Systems
July 11 5:00pm - 6:00pm Engineering Poster Track Automated Timing-aware Dynamic Voltage Drop ECO Seonghun Jeong - Samsung Electronics
Dongyoun Yi - Samsung Electronics
Byunghyun Lee - Samsung Electronics
Sun ik Heo - Samsung Electronics
Len Hsu - Synopsys
KH Kim - Synopsys
Anusha Gummana – Ansys
Jie Cheng - Ansys
Sankar Ramachandran – Ansys
July 11 5:00pm - 6:00pm Engineering Poster Track Power solution to maximize performance-per-watt for GPGPU Shixuan Que - Iluvatar
Ling Sun - Iluvatar
Lili Dai - Iluvatar
Yuanyuan Ling - Iluvatar
Zhenbang Wang - Ansys
July 11 5:00pm - 6:00pm Engineering Poster Track Power-Thermal Co-simulation for More Accurately DC IR Drop and temperature distribution of GPGPU’s PCB and Package Shuyuan Guan - Birentech
Zhenghao Chu - Ansys
July 11 5:00pm - 6:00pm Engineering Poster Track DVD Diagnostics - Debugging Dynamic IR problems using Advanced Analytics

Ilhan Hatirnaz – NXP Semiconductors
Manmeet Singh– Ansys

July 12 10:30am - 10:45am Engineering Track Prototyping and verification of Power Delivery network for a Foveros 3DIC design Amartya Mazumdar - Intel
Vineet Sreekumar - Intel
Basavaraj Kanthi - Intel
Chandrahas Alla - Intel
Manish Kumar - Intel
Alina SebastianIntel Corporation
Tapan GanpuleIntel Corporation
July 12 11:15am - 11:30am Engineering Track RTL Design Security Verification for Resisting Power Side-Channel Analysis
Kazuki Monta - Kobe University
Makoto Nagata - Kobe University
Lang Lin – Ansys
Jimin Wen – Ansys
Preeti Gupta – Ansys
Norman Chang - Ansys
July 12 11:30am – 11:45am Engineering Track IR drop fixing using Timing ECO integrated solution with IR Signoff tool Sahil Sukheja – Google
Amruthavalli Sreekantapuram – Google
Mathew Kaipanatu - Google
July 12 11:45am – 12:00am Engineering Track
SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff Anusha Vemuri - NVIDIA
Emmanuel Chao - NVIDIA
Santosh Santosh - NVIDIA
Piyush Jain - Ansys
Yatender Mishra - Ansys
July 12 5:00pm – 6:00pm Engineering Poster Track A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design Yaping Huang - Sanechips
Kai Fang - Sanechips
Hong Jia - Ansys
July 12 5:00pm – 6:00pm Engineering Poster Track Thermal Aware Memory Controller Design with Chip Package System Simulation Shiva Shankar Padakanti - Micron
Ravi Kollipara – Micron
Dileesh Jostin - Ansys
Vamsi Krishna - Ansys
July 12 5:00pm – 6:00pm Engineering Poster Track Towards an Automated Workflow for Link-level Exploration and Optimization in the Domain of All-to-All Optical Networks Luca Ramini - Hewlett Packard Enterprise
Ahsan Alam - Ansys
July 12 5:00pm – 6:00pm Engineering Poster Track In-design IR drop convergence with Ansys RHSC and SNPS fusion compiler Purushotham Reddy - Intel
Usha Muruli - Intel
July 12 5:00pm – 6:00pm Engineering Poster Track Concurrent Package + Interposer + Die IR Analysis using Ansys’ RedHawk-SC Electrothermal Nikhil Jayakumar - Amazon
July 12 5:00pm - 6:00pm Engineering Poster Track Building a Robust Power Grid for Multi Million SoC using RedHawk-SC Early PG Grid Analysis

Rishikanth Mekala – Samsung Semiconductor
Arpan Bhowmik – Samsung Semiconductor
Krishna Yellamilli – Ansys

July 12 5:00pm - 6:00pm Engineering Poster Track A High-Accuracy Voltage-Aware-Timing Solution for HPC Design

Xiyu Wang – ZTE Technology Co., Ltd.
Zhijun Long – Sanechips Technology Co.,Ltd
Keqing Ouyang – Sanechips Technology Co.,Ltd
Junjie Chen – Sanechips Technology Co.,Ltd
Ping Ding – Sanechips Technology Co.,Ltd
Dongli Song – Synopsys
Chang Zhao – Ansys
Li Zou –Ansys
Muhammad Zakir – Ansys

July 13 1:30pm – 1:45pm Engineering Track Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution Shixuan Que - Iluvatar
Ling Sun - Iluvatar
Lili Dai - Iluvatar
Yuanyuan Ling - Iluvatar
Zhenbang Wang - Ansys
July 13 2:30pm – 2:45pm Engineering Track Thermal Tuning Power Budgeting with Statistical and Temperature Variation for Microring-Based DWDM 3D Silicon Photonics Jinsung Youn - Hewlett Packard Enterprise
Marco Fiorentino - Hewlett Packard Enterprise
Ahsan Alam - Ansys
Leanne Dias - Ansys
Zeqin Lu - Ansys
James Pond - Ansys
Norman Chang - Ansys
Raymond Beausoleil - Hewlett Packard Enterprise