Next-generation field programmable gate arrays (FPGAs) for 5G, AI, automotive, cloud and data center applications are getting bigger, faster and more complex. With the market’s continuous demand for higher performance and lower power products, FPGA designers strive hard to achieve stringent power, performance, area and reliability goals to stay ahead of the game. Traditional electronic design automation (EDA) techniques for full-chip critical path timing analysis and power integrity signoff cannot meet the capacity, performance and accuracy requirements for these complex FPGAs. Productivity and project schedules are negatively impacted as a result.
In this webinar, FPGA inventor Xilinx will discuss the many applications for its innovative elastic compute scalable design methodologies, including:
- Large design scaling for timing analysis using ANSYS SeaScape
- Full-chip EM/IR signoff using ANSYS RedHawk-SC
- Accelerated chip-scale interconnect delay calculation for timing capture flow using ANSYS Path
Nitin Navale, CAD Manager, Xilinx
Nitin oversees CAD development for a wide range of topics including timing analysis, EM/IR and chip-level construction. He also participates in methodology related to topics like simulation, extraction, thermal analysis and ESD. He earned his B.S. and M.S. degrees in electrical engineering from the University of Illinois, Urbana-Champaign. Before Xilinx, he worked at AMD where he specialized in CAD development for EM/IR and ESD.
Karan Sahni, Senior Area Technical Manager, ANSYS
Karan Sahni joined ANSYS as a result of Apache acquisition in 2011. As of 2017 Karan has been serving as Sr Manager of Application Engineering in the Semiconductor Business Unit. He and his team support Ansys-SCBU customers in the silicon valley region. He received his MS in Electrical Engineering from Syracuse University NY and BE in Electronics & Communication from Rajasthan University in India.