Chip-package co-simulation for 2.5DIC with HBM

Accelerating 5G Design Innovation Through Simulation Workshop

January 29, 2019

1:30 PM - 5:30 PM (PST)


Hyatt Regency
5101 Great America Parkway
Santa Clara, CA 95054
Room: Bayshore East/West

Verly Flores

The next generation of wireless technology - driven by 5G – will transform the way we communicate, commute and collaborate with machines and humans alike in the near future. Ubiquitous connectivity, low latency and faster data rates are going to enable billions of more smart devices. These devices will be generating more data at the edge, transporting more data across the network and processing more data both at the edge and in the cloud. 5G network infrastructure will rely on high-frequency mmWave spectrum, massive MIMO, small cells and beamforming and beam tracking capabilities that will increasingly complicate the design of these electronics systems that must now absorb huge amounts of antenna data, support a variety of 5G air interfaces – such as massive Machine Type Communication (MTC), enhanced Mobile Broadband (eMBB), and Ultra-Reliable Communication (URC) and Low Latency – and offer significantly higher processing capabilities within a power and thermal constrained environment.

Electronics systems for 5G infrastructure will require fully integrated mmWave RF solution, advanced SoCs and state of the art 3D-IC and fan-out wafer-level packaging (FOWLP) technologies to deliver the required performance, power, system bandwidth and low latency. For these system-in-package designs, the chip needs to be designed in the context of the package and the overall system to deliver the highest performance for processing the huge amounts of data at lightning speed. Power integrity and signal integrity are critical for ensuring product success; however, they become increasingly challenging to achieve for these advanced system-in-package and 3D-IC designs. Also, addressing reliability challenges – including electromigration (EM), thermal-aware EM, thermal-induced mechanical stress, ESD and device aging- are key for 5G electronics systems that will enable mission-critical applications of the future like self-driving cars.

Attend this workshop to learn how ANSYS simulations can help you accelerate 5G design innovation across the spectrum of chip, package and system (CPS). Topics will cover simulation solutions for RF and antenna designs, electronics system reliability and chip-package-system co-analysis for power integrity sign-off for advanced packaging technologies – 3D-IC and FOWLP. Don’t miss this exciting opportunity to meet industry experts and get ahead in the race for 5G with ANSYS simulations.

DesignCon badge is NOT required, but pre-registration is a must to attend this workshop.


Time Topic
1:30 - 1:45 PM ANSYS Introduction and Welcome
Rajeev Rajan, Senior Director Solutions Marketing, ANSYS
1:45 - 2:15 Keynote: GlobalFoundries
Peter A. Rabbeni, VP RF Offering Management, Business Development and Marketing, GlobalFoundries
2:15 - 2:45 Accelerating 5G Design Innovation Through Simulation
Dr. Larry Williams, Director of Technology, ANSYS
2:45 - 3:15 Achieving Electronics System Reliability for 5G Designs
Dr. Norman Chang, Chief Technologist, Semiconductors, ANSYS
3:15 - 3:30 Networking Break
3:30 - 4:00 Addressing Multi-Die Power Integrity Challenges for 5G Applications with Chip, Package and System Co-Simulation
Chris Ortiz, Principal Application Engineer, Semiconductors, ANSYS
4:00 - 4:30 Addressing Signal and Power Integrity Challenges of DDR5 Memory for Enabling High Speed 5G Applications
Jonghyun Cho, SMTS II Signal Integrity Engineer, Rambus
4:30 - 5:30 Networking Reception & Raffle