Ansys Clock Jitter Flow: Build Semiconductor Simulation Expertise at Your Pace

Training and certification courses help us grow our productivity, develop new skillsets, and prepare us for emerging industry trends and technologies. Whether virtual or in person, attendees benefit from instructor-led training and interacting directly with experts during the training session. But this often comes at the cost of convenience — the attendee must dedicate time and attend the training at the reserved time slot, which could take either a half- or full day. Due to our busy schedules, we often either partially attend or miss the session entirely due to short-term priority changes.

A self-paced course returns convenience to its attendees by letting them learn at their own pace. Self-paced courses are often heavily modularized, with each module focusing on a specific micro topic in detail by covering information in small increments. Thus, users can reserve a fixed time slot per day to cover a module and complete the course at their convenience.

Capitalizing on the benefits of self-paced training, Ansys has launched its first self-paced course on semiconductor dynamic voltage drop (DVD)-induced clock jitter.

Clock signals are the “arteries” of the modern system-on-chips (SoCs). Clock speed refers to the rate at which a computer’s central processing unit (CPU) executes instructions, and it is a measure of the performance and market success of every semiconductor product. Every semiconductor design house desires higher chip performance, which can be achieved by increasing clock speed. To achieve greater clock speeds, we need to ensure that the clock jitter and clock skew are under check. While clock skew refers to spatial deviation in the clock arrival time, clock jitter refers to an undesirable temporal deviation of the clock signal at a specific destination. Jitter is a more critical issue due to its temporal nature and impact on the clock period.

Clock jitter can arise due to a broad range of reasons, from material imperfection to variations in device manufacturing, crosstalk, and even DVD. As we move toward advanced technology nodes to achieve higher clock speeds, the power supply voltage gets scaled down to meet the power efficiency. The reduced supply voltage and increased voltage (IR) drop drives clock instances toward near-threshold voltage operations, leading to non-Gaussian variation in the cell delay that results in DVD-induced jitter. This challenge requires a simulation-based approach to resolve.

Ansys RedHawk-SC is the industry gold standard in SOC power-noise and reliability signoff. RedHawk-SC is built on Ansys SeaScape, the world's first purpose-built, big-data architecture for multiphysics simulations. SeaScape framework provides per-core scalability, flexible design data access, instantaneous design bring-up, data analytics, and many other revolutionary capabilities. Ansys Clock FX built on top of FX technology can simulate the entire clock tree of SOC design to evaluate the DVD impact on jitter with SPICE-level accuracy. Through its distributed architecture, Clock FX maintains SPICE accuracy in jitter results in a fraction of the time required by SPICE simulators and with significantly less setup effort. Unlike traditional static timing analysis (STA)-based solutions that work on arc voltages, Clock FX can model voltage drop and ground bounce separately and generate a rich set of jitter reports covering several jitter types.

Clock FX jitter flow can be seamlessly integrated with existing DVD signoff methodology. It can natively hand off DVD information from RedHawk-SC to perform jitter simulation. After the simulations are run, the results can be seamlessly back-annotated onto RedHawk-SC, enabling you to visualize jitter and DVD results. The built-in data analytics capabilities of RedHawk-SC allows the designers to analyze jitter bottlenecks and make critical design decisions.

To learn more about Ansys clock jitter flow, take the "Ansys RedHawk-SC
Clock Jitter Flow" self-paced course.