Ansys Totem-SC is the proven, trusted industry leader for power noise and reliability signoff for analog and mixed-signal designs built on cloud-native elastic compute infrastructure.
Ansys Totem-SC is the industry’s trusted gold standard voltage drop and electromigration multiphysics sign-off solution for transistor-level and mixed-signal designs. With a track record of thousands of tapeouts, Totem-SC’s cloud-based architecture gives it the speed and capacity to handle full-chip analysis. Signoff accuracy is certified by all major foundries for all finFET nodes down to 3nm.
Ansys Totem-SC is a transistor-level power noise and reliability analysis platform for analog mixed-signal IP and fully custom designs. It creates IP models for SOC-level power integrity signoff with RedHawk-SC and generates compact chip models of power delivery networks for the chip and system-level.
NXP engineers design a chip for digital automobile radio with lower costs and superior sound quality.
Signoff analysis reduces project risk by avoiding costly errors in silicon. Accurate multiphysics simulation improves design performance by eliminating wasteful margin with better silicon correlation.
Ansys Totem-SC’s trusted multiphysics signoff analysis is a powerful way to reduce project and technology risk. Totem-SC’s algorithms are certified accurate by all major foundries for all finFET processes and are proven in thousands of tapeouts.
The speed and capacity of Totem-SC’s cloud-native SeaScape™ architecture enable ultra-large, full-chip power analyses by enlisting thousands of CPU cores with modest memory requirements. Totem’s advanced reliability analyses—like thermal-aware EM and statistical EM budgeting—improve the safety of automotive designs
Ansys Totem-SC provides value from early IC prototyping stages all the way to the system level. Early analysis enables cheaper and more impactful optimizations than are possible at signoff. The foundry-certified silicon-correlated simulation results give designers the confidence they need to achieve higher performance and lower power by avoiding wasteful and expensive overdesign.
Ansys Totem-SC is a transistor-level power noise and reliability analysis platform for comprehensive power integrity analysis on analog mixed-signal IP and full custom designs. Totem can create IP models for SoC-level signoff using RedHawk-SC. Totem-SC analyses span early prototype to signoff and can handle a variety of design styles such as SerDes, data converters, power management IC, embedded memories, DRAM, Flash, FPGA and image sensors. It analyzes substrate noise, RDSON, self-heat and ESD (with Ansys PathFinder™). Totem-SC’s cloud-native elastic compute architecture has the capacity to handle very large designs with modest memory overhead.
Ansys Totem-SC sets the standard for analog mixed-signal signoff.
Ansys Totem-SC offers capabilities like power grid weakness analysis, missing vias, P2P checks and a variety of early-stage static and dynamic IR and EM analysis that can highlight design weaknesses in early design stages before a design is LVS clean. These allow designers to decide on power grid planning, bump placement, decoupling cap optimization and EM on critical nets.
Ansys Totem-SC accurately signs off large, mixed-signal designs. Key features like native handling of the place and route digital database and hierarchical analysis of complex AMS simplifies the overall flow with a bottom-up validation of each block and a comprehensive multi-state transistor level or abstracted macro-model for top- level analysis. Vectored or vectorless simulations can align functional states to mimic worst case stress scenarios.
Ansys Totem provides a comprehensive EM signoff that includes power/signal EM analysis, modeling joule-heating, wire coupling and self-heating of the FinFETs and their impact on the interconnects. The flow is enabled by all major foundries and used by all customers doing FinFET designs. Statistical EM Budgeting is also enabled in Totem to address demands for automotive and other mission critical applications.
IP integration is one of the biggest challenges faced by SoC designers. The same IP operating in two different modes can experience very different voltage drop. Totem-SC accurately models and characterizes IP for different modes of operation in top-level voltage drop analysis. The IP model includes electrical and physical properties, along with any embedded constraints for power integrity signoff at the SoC level by Ansys RedHawk-SC.
Ansys Totem-SC’s GUI offers advanced query and debugging capabilities, including customizable maps and debug views to help identify and fix design weakness. Totem-SC also enables what-if analyses to make quick design fixes before finalizing changes in the design. This significantly speeds up the turnaround, compared to traditional flows where fixes first need to pass through expensive LVS and RC extraction before doing EM/IR analysis.
Ansys Totem-SC is built on the SeaScape big data analytics platform that is designed for cloud execution on thousands of CPU cores with near linear scalability and extremely high capacity with low memory per core.
