Accelerating ESD Simulation for Full-Chip and Multi-Die 3D-IC Design

Overview

As semiconductor complexity accelerates with advanced nodes, chiplets, and 3DIC integration, robust ESD protection requires verification earlier in the flow. PathFinder-SC shifts signoff simulations to the design stage earlier using cell-based modeling of discharge circuits  derived from GDS/OASIS of design and/or Place&Route design data (DEF/LEF). This combines certified accuracy with cloud-native capacity to handle effective resistance, current density, and CDM checks across full-chip and multi-die designs. PathFinder-SC utilizes the same extraction and EM calculation engine as Redhawk-SC, certified by major foundries, which can help detect potential silicon failures. Its layout-based debugging and compact modeling extend reliability from die to package to board. Seamlessly integrated into modern verification flows, PathFinder-SC empowers teams to accelerate signoff, mitigate risk, and deliver future-proof designs for HPC, AI/ML, and 5G/6G systems.

What Attendees Will Learn

• Cell-based modeling of clamps from GDS/OASIS and/or P&R tool DEF/LEF
• Overview of static ESD simulation checks handled by PathFinder-SC for fullchip, interposer and multi-die designs
• Performance overview and future road map sharing
• Debug and diagnostic capabilities

Who Should Attend

• ESD Expert
• IC Design Engineers (Analog, Mixed-Signal, and Digital)
• Verification and Signoff Engineers
• EDA/Tool Evaluation Teams
• Product/Project Managers in Semiconductor Companies
• Advanced Node/3DIC/Chiplet Architects

Speakers

• John Alwyn - Senior Principal Product Specialist SCBU, Ansys
• Marc Swinnen - Senior Principal Product Marketing Manager, Ansys